Hierarchical scan architecture for design for test applications

• US 6,106,568 A
• Filed: 06/03/1999
• Issued: 08/22/2000
• Est. Priority Date: 08/28/1996
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Robinson, Markus F., Ellingham, Chris, Walker, Robert, Beausang, James
• Primary Examiner(s): Lintz, Paul R.
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/324,755
• Time in Patent Office: 446 Days
• Field of Search: 395/500.02-500.19, 716/1-21
• US Class Current: 716/102
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals

Abstract

A system and method for architecting design for test circuitry (e.g., scan architecting) within an integrated circuit design having subdesigns (e.g., modules). The novel system contains a default operational mode (no user specification) and an operational mode based on user specifications; within either mode, the system recognizes and allows definition of subdesign scan chains which can be linked together alone or with other scan elements to architect complex scan chains (e.g., top level scan chains). The system includes specification, analysis, synthesis and reporting processes which can be used in an IC design having a hierarchical structure including modules. The specification process accesses a design database and a script file and allows a user to define global scan properties (scan style, number of chains, etc.), properties of a particular scan chain (membership, name, etc.), test signals (scan-in, scan-out, scan-enable, etc.), complex elements used as part of a scan chain without requiring scan replacement, wires and latches forming connections between scan elements; this information is associated with the selected design database. Analysis reads the design database and performs architecting of scan chains based on inferred scan elements of the design and defined (e.g. specified) scan elements. During analysis, the logic within the design database is not altered and a script is generated for user modification/verification. Specification and analysis can be executed iteratively until the desired scan structures are planned. Synthesis then implements the desired DFT circuitry by altering the design database based on the scan chains planned by analysis.

Claims

1. A computer readable medium containing instructions that when executed implement a method of inserting scan resources into an integrated circuit design, said method comprising the steps of:

a) accessing user defined specification commands defining scan configurations that indicate a manner in which scan chains are to be constructed and define scan structures to be used in constructing said scan chains;

b) generating a scan plan based on said design and based on said specification commands without altering logic within said design, said step b) further comprising the steps of;

b1) partially constructing scan chains within said scan plan according to said specification commands;

b2) identifying scan structure within said design not covered by said specification commands; and

b3) completely constructing said scan chains within said scan plan based on said scan structure identified in steps b1) and b2) to generate balanced scan chains; and

c) synthesizing said scan plan within said design by inserting scan resources into said design to realize said balanced scan chains, said step c) storing information in computer memory for use by a computer system in the production of an integrated circuit device of said integrated circuit design.

2. A computer readable medium as described in claim 1 wherein said step b) of said method further comprises the step of generating a report of scan resources to be constructed within said design based on said scan plan.

3. A computer readable medium as described in claim 1 wherein said method further comprises the step of d) generating a report indicating existing scan resources within said design.

4. A computer readable medium as described in claim 1 wherein said step b3) of said method further comprises the steps of:

integrating scan structure identified in step b2) within partially constructed scan chains of step b1); and

constructing additional scan chains composed of said scan structure identified in step b2).

5. A computer readable medium as described in claim 1 wherein said step a) of said method further comprises the step of receiving a specification command defining a scan segment, said scan segment including a member list of sequentially coupled scan cells and access points to said member list, said access points including a scan in and scan out.

6. A computer readable medium as described in claim 1 wherein said step a) of said method further comprises the step of receiving a specification command defining a scan path, said scan path including a list of scan structures to be linked together by step b) and by step c) to form a scan chain of said scan structures.

7. A computer readable medium as described in claim 1 wherein said step a) of said method further comprises the step of receiving a specification command defining a scan configuration, said scan configuration including a number of said scan chains to be constructed by said step b) and by said step c) and further including an indication of whether or not clock domain mixing is allowed by said step b) and by said step c) in constructing said balanced scan chains.

8. A computer readable medium containing instructions that when executed implement a method of inserting scan resources into an integrated circuit design, said method comprising the steps of:

a) accessing user defined specification commands defining scan configurations that indicate a manner in which scan chains are to be constructed and define scan structures to be used in constructing said scan chains, wherein said specification commands include a specification command defining a scan segment, said scan segment including a member list of sequentially coupled scan cells and access points to said member list, said access points including a scan in and scan out;

b) generating a scan plan based on said design and based on said specification commands without altering logic within said design, said step b) further comprising the steps of;

b1) partially constructing scan chains within said scan plan according to said specification commands;

b2) identifying scan structure within said design not covered by said specification commands; and

b3) completely constructing said scan chains within said scan plan based on said scan structure identified in steps b1) and b2) to generate balanced scan chains; and

c) synthesizing said scan plan within said design by inserting scan resources into said design to realize said balanced scan chains, said step c) storing information in computer memory for use by a computer system in the production of an integrated circuit device of said integrated circuit design.

9. A computer readable medium as described in claim 8 wherein said step b) of said method further comprises the step of generating a report of scan resources to be constructed within said design based on said scan plan.

10. A computer readable medium as described in claim 9 wherein said method further comprises the step of d) generating a report indicating existing scan resources within said design.

11. A computer readable medium as described in claim 8 wherein said step b3) of said method further comprises the steps of:

integrating scan structure identified in step b2) within partially constructed scan chains of step b1); and

constructing additional scan chains composed of said scan structure identified in step b2).

12. A computer readable medium as described in claim 8 wherein said step a) of said method further comprises the step of receiving a specification command defining a scan path, said scan path including a list of scan structures to be linked together by step b) and by step c) to form a scan chain of said scan structures.

13. A computer readable medium as described in claim 12 wherein said step a) of said method further comprises the step of receiving a specification command defining a scan configuration, said scan configuration including a number of said scan chains to be constructed by said step b) and by said step c) and further including an indication of whether or not clock domain mixing is allowed by said step b) and by said step c) in constructing said balanced scan chains.

14. An apparatus for inserting scan resources into an integrated circuit design comprising:

a) means for accessing user defined specification commands defining scan configurations that indicate a manner in which scan chains are to be constructed and define scan structures to be used in constructing said scan chains;

b) means for generating a scan plan based on said design and based on said specification commands without altering logic within said design, said means for generating a scan plan comprising;

b1) means for partially constructing scan chains within said scan plan according to said specification commands;

b2) means for identifying scan structure within said design not covered by said specification commands; and

b3) means for completely constructing said scan chains within said scan plan based on said scan structure identified in said means for partially constructing and said means for identifying scan structure to generate balanced scan chains; and

c) means for synthesizing said scan plan within said design by inserting scan resources into said design to realize said balanced scan chains, said means for synthesizing also for storing information in computer memory for use by a computer system in the production of an integrated circuit device of said integrated circuit design.

15. An apparatus as described in claim 14 wherein said means for generating a scan plan further comprises means for generating a report of scan resources to be constructed within said design based on said scan plan.

16. An apparatus as described in claim 15 and further comprising means for generating a report indicating existing scan resources within said design.

17. An apparatus as described in claim 14 wherein said means for completely constructing said scan chains comprises:

means for integrating scan structure identified in said means for identifying scan structure within partially constructed scan chains of said means for partially constructing scan chains; and

means for constructing additional scan chains composed of said scan structure identified in said means for identifying scan structure.

18. An apparatus as described in claim 14 wherein said means for accessing further comprises means for receiving a specification command defining a scan segment, said scan segment including a member list of sequentially coupled scan cells and access points to said member list, said access points including a scan in and scan out.

19. An apparatus as described in claim 14 wherein said means for accessing further comprises means for receiving a specification command defining a scan path, said scan path including a list of scan structures to be linked together by said means for generating a scan plan and by said means for synthesizing said scan plan to form a scan chain of said scan structures.

20. An apparatus as described in claim 14 wherein said means for accessing further comprises means for receiving a specification command defining a scan configuration, said scan configuration including a number of said scan chains to be constructed by said means for generating a scan plan and by said means for synthesizing said scan plan and further including an indication of whether or not clock domain mixing is allowed by said means for generating a scan plan and by said means for synthesizing said scan plan in constructing said balanced scan chains.