CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions

• US 6,107,130 A
• Filed: 11/10/1998
• Issued: 08/22/2000
• Est. Priority Date: 12/06/1996
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wristers, Derick J., Gardner, Mark I., Fulford, H. Jim Jr.
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US09/189,235
• Time in Patent Office: 651 Days
• Field of Search: 438/229, 438/230, 438/231, 438/232, 438/275, 438/304, 438/305, 438/529
• US Class Current: 438/231
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

An integrated circuit is formed whereby junction of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD area, an MDD area and a heavy concentration source/drain area. Conversely, the PMOS transistor include an LDD area and a source/drain area. The NMOS transistor junction is formed dissimilar from the PMOS transistor junction to take into account the less mobile nature of the junction dopants relative to the PMOS dopants. Thus, a lessening of the LDD area and the inclusion of an MDD area provide lower source/drain resistance and higher ohmic connectivity in the NMOS device. The PMOS junction includes a relatively large LDD area so as to draw the highly mobile, heavy concentration boron atoms away from the PMOS channel.

Claims

1. A method for forming a CMOS integrated circuit, comprising:

patterning a first gate conductor between opposing sidewall surfaces across a first channel portion of a semiconductor topography;

using the first gate conductor as a mask, implanting a first n-type dopant into said semiconductor topography adjacent said channel portion;

forming a dielectric spacer upon the sidewall surfaces;

using the dielectric spacer and the first gate conductor as a mask, implanting a second n-type dopant into said semiconductor topography a first spaced distance from said channel portion;

forming a conductive spacer upon the dielectric spacer; and

using the conductive spacer, the dielectric spacer and the first gate conductor as a mask, implanting a third n-type dopant into said semiconductor topography a second spaced distance greater than the first spaced distance from said channel portion.

2. The method as recited in claim 1, wherein said first n-type dopant is implanted at a lesser concentration and at a lesser energy into said semiconductor substrate than said second n-type dopant, and wherein said second n-type dopant is forwarded at a lesser concentration and at a lesser energy into said semiconductor substrate than said third n-type dopant.

3. The method as recited in claim 1, wherein said first n-type dopant comprises phosphorous, and wherein said second and third n-type dopant comprises arsenic.

4. The method as recited in claim 1, wherein forming said conductive spacer comprises depositing a metal layer upon the dielectric spacer and anisotropically removing the metal layer except immediately adjacent said dielectric spacer.

5. The method as recited in claim 1, further comprising:

patterning a second gate conductor across a second channel portion of the semiconductor topography a lateral spaced distance from the first gate conductor, wherein the second gate conductor comprises opposing second sidewall surface between which the second gate conductor is confined;

using the second gate conductors as a mask, implanting a first p-type dopant into said semiconductor topography adjacent said second channel portion;

forming the dielectric spacer and the conductive spacer upon the second sidewall surfaces; and

using the conductive spacer, the dielectric spacer and the second gate conductor as a mask, implanting a second p-type dopant into said semiconductor topography a first spaced distance from said second channel portion.

6. The method as recited in claim 5, wherein said first p-type dopant is implanted at a lesser concentration and at a lesser energy into said semiconductor substrate than said second p-type dopant.

11. The method as recited in claim 1, further comprising removing the conductive spacer subsequent to said implanting a third n-type dopant.

12. The method as recited in claim 1, wherein said sidewall surfaces comprise thermally oxidized polycrystalline silicon.

13. The method as recited in claim 1, wherein said conductive spacer comprises metal selected from the group consisting of tungsten, titanium and aluminum.

14. The method as recited in claim 1, further comprising forming silicide upon and into said semiconductor topography.

15. The method as recited in claim 5, wherein an as-implanted p-type lightly doped drain region formed by said implanting a first p-type dopant and a second p-type dopant has a greater lateral width than an as-implanted n-type lightly doped drain region formed by said implanting a first n-type dopant and a second n-type dopant.

7. A method for forming an integrated circuit, comprising:

patterning a first gate conductor having opposed sidewall surfaces across a first channel portion of a dielectric covered semiconductor substrate;

forming a dielectric spacer upon the sidewall surfaces and a conductive spacer upon the dielectric spacer;

using the conductive spacer, the dielectric spacer and the gate conductor as a mask, implanting into said semiconductor substrate n-type dopants at a first concentration;

using the dielectric spacer as an etch stop, removing the conductive spacer;

using the dielectric spacer and the gate conductor as a mask, implanting into said semiconductor substrate n-type dopants at a second concentration less than the first concentration;

using the gate conductor as an etch stop, removing the dielectric spacer; and

using the gate conductor as a mask, implanting into said semiconductor substrate n-type dopants at a third concentration less than the second concentration.

8. The method as recited in claim 7, wherein said sidewall surfaces comprise thermally oxidized polycrystalline silicon.

9. The method as recited in claim 7, wherein said conductive spacer comprises metal.

10. The method as recited in claim 7, further comprising forming silicide upon and into said semiconductor substrate.

16. The method as recited in claim 7, farther comprising:

patterning a second gate conductor having opposed sidewall surfaces a lateral spaced distance from the first gate conductor across a second channel portion of the semiconductor substrate;

forming a dielectric spacer upon the sidewall surfaces and a conductive spacer upon the dielectric spacer;

using the conductive spacer, the dielectric spacer and the second gate conductor as a mask, implanting into said semiconductor substrate p-type dopants at a first concentration;

using the dielectric spacer as an etch stop, removing the conductive spacer;

using the second gate conductor as an etch stop, removing the dielectric spacer; and

using the second gate conductor as a mask, implanting into said semiconductor substrate p-type dopants at a second concentration less than the first concentration.

17. The method as recited in claim 10, further comprising removing the conductive spacer either during formation of the silicide or by using a wet etch process.

18. The method as recited in claim 7, wherein said first and second n-type dopant comprises phosphorous, and wherein said third n-type dopant comprises arsenic.

19. The method as recited in claim 7, wherein forming said conductive spacer comprises depositing a metal layer upon the dielectric spacer and anisotropically removing the metal layer except immediately adjacent said dielectric spacer.

20. The method as recited in claim 7, wherein an as-implanted p-type lightly doped drain region formed by said implanting a first p-type dopant and a second p-type dopant has a greater lateral width that an as-implanted n-type lightly doped drain region formed by said implanting a second n-type dopant and a third n-type dopant.