Self-aligned methods of fabricating silicon carbide power devices by implantation and lateral diffusion
First Claim
1. A method of fabricating a silicon carbide power device comprising the steps of:
- masking a surface of a silicon carbide substrate to define an opening at the surface;
first implanting p-type dopants into the silicon carbide substrate through the opening at implantation energy and dosage that form a deep p-type implant;
then implanting n-type dopants into the silicon carbide substrate through the opening at implantation energy and dosage that form a shallow n-type implant relative to the deep p-type implant;
annealing at temperature and time that is sufficient to laterally diffuse the deep p-type implant to the surface of the silicon carbide substrate surrounding the shallow n-type implant, without vertically diffusing the deep p-type implant to the surface of the silicon carbide substrate through the shallow n-type implant; and
implanting a p-type well at the surface of the silicon carbide substrate, electrically contacting the laterally diffused deep p-type implant.
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Accused Products
Abstract
Silicon carbide power devices are fabricated by implanting p-type dopants into a silicon carbide substrate through an opening in a mask, to form a deep p-type implant. N-type dopants are implanted into the silicon carbide substrates through the same opening in the mask, to form a shallow n-type implant relative to the p-type implant. Annealing is then performed at temperature and time that is sufficient to laterally diffuse the deep p-type implant to the surface of the silicon carbide substrate surrounding the shallow n-type implant, without vertically diffusing the p-type implant to the surface of the silicon carbide substrate through the shallow n-type implant. Accordingly, self-aligned shallow and deep implants may be performed by ion implantation, and a well-controlled channel may be formed by the annealing that promotes significant diffusion of the p-type dopant having high diffusivity, while the n-type dopant having low diffusivity remains relatively fixed. Thereby, a p-base may be formed around an n-type source. Lateral and vertical power MOSFETs may be fabricated.
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Citations
46 Claims
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1. A method of fabricating a silicon carbide power device comprising the steps of:
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masking a surface of a silicon carbide substrate to define an opening at the surface; first implanting p-type dopants into the silicon carbide substrate through the opening at implantation energy and dosage that form a deep p-type implant; then implanting n-type dopants into the silicon carbide substrate through the opening at implantation energy and dosage that form a shallow n-type implant relative to the deep p-type implant; annealing at temperature and time that is sufficient to laterally diffuse the deep p-type implant to the surface of the silicon carbide substrate surrounding the shallow n-type implant, without vertically diffusing the deep p-type implant to the surface of the silicon carbide substrate through the shallow n-type implant; and implanting a p-type well at the surface of the silicon carbide substrate, electrically contacting the laterally diffused deep p-type implant. - View Dependent Claims (2, 3, 4, 5, 6, 45)
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7. A method of fabricating a silicon carbide power device comprising the steps of:
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masking a surface of a silicon carbide substrate to define an opening at the surface; first implanting n-type dopants into the silicon carbide substrate through the opening at implantation energy and dosage that form a shallow n-type implant; electrically activating the n-type dopants; then implanting p-type dopants into the silicon carbide substrate through the opening at implantation energy and dosage that form a deep p-type implant relative to the shallow n-type implant; annealing at temperature and time that is sufficient to laterally diffuse the deep p-type implant to the surface of the silicon carbide substrate surrounding the shallow n-type implant, without vertically diffusing the deep p-type implant to the surface of the silicon carbide substrate through the shallow n-type implant; and implanting a p-type well at the surface of the silicon carbide substrate, electrically contacting the laterally diffused deep p-type implant. - View Dependent Claims (8, 9, 10, 11, 12, 46)
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13. A method of fabricating a silicon carbide lateral power MOSFET comprising the steps of:
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implanting an aluminum well into a drift region at a surface of a silicon carbide substrate; masking the drift region at the surface of the silicon carbide substrate to define a first pair of openings on the drift region, a respective one of which is on a respective opposite side of the aluminum well; first implanting p-type dopants into the silicon carbide substrate through the first pair of openings at implantation energy and dosage that form deep p-type implants; then implanting n-type dopants into the silicon carbide substrate through the first pair of openings at implantation energy and dosage that form shallow n-type implant relative to the deep p-type implants; masking the drift region at the surface of the silicon carbide substrate to define a second pair of openings on the drift region, a respective one of which is spaced apart from a respective shallow n-type implant and opposite the aluminum well; implanting n-type dopants into the silicon carbide substrate through the second pair of openings to define a pair of drain regions; annealing at temperature and time that is sufficient to laterally diffuse the respective deep p-type implants to the surface of the silicon carbide substrate surrounding the respective shallow n-type implants, without vertically diffusing the respective deep p-type implants to the surface of the silicon carbide substrate through the respective shallow n-type implants, to thereby form a pair of channel regions in the laterally diffused p-type implants at the surface of the silicon carbide substrate, a respective one of which is on a respective opposite side of the aluminum well; forming a pair of gate insulating regions on the drift region at the surface of the silicon carbide substrate, a respective one of which contacts a respective one of the pair of channel regions; and forming a common source contact, a pair of drain contacts and a pair of gate contacts on the shallow n-type implants and the aluminum well therebetween, on the drain regions, and on the pair of gate insulating regions, respectively. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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22. A method of fabricating a silicon carbide lateral power MOSFET comprising the steps of:
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implanting an aluminum well into a drift region at a surface of a silicon carbide substrate; masking the drift region at the surface of the silicon carbide substrate to define a first pair of openings on the drift region, a respective one of which is on a respective opposite side of the aluminum well; first implanting n-type dopants into the silicon carbide substrate through the first pair of openings at implantation energy and dosage that form shallow n-type implants; electrically activating the n-type dopants; then implanting p-type dopants into the silicon carbide substrate through the first pair of openings at implantation energy and dosage that form deep p-type implants relative to the shallow n-type implants; masking the drift region at the surface of the silicon carbide substrate to define a second pair of openings on the drift region, a respective one of which is spaced apart from a respective shallow n-type implant and opposite the aluminum well; implanting n-type dopants into the silicon carbide substrate through the second pair of openings to define a pair of drain regions; annealing at temperature and time that is sufficient to laterally diffuse the respective deep p-type implants to the surface of the silicon carbide substrate surrounding the respective shallow n-type implants, without vertically diffusing the respective deep p-type implants to the surface of the silicon carbide substrate through the respective shallow n-type implants, to thereby form a pair of channel regions in the laterally diffused p-type implants at the surface of the silicon carbide substrate, a respective one of which is on a respective opposite side of the aluminum well; forming a pair of gate insulating regions on the drift region at the surface of the silicon carbide substrate, a respective one of which contacts a respective one of the pair of channel regions; and forming a common source contact, a pair of drain contacts and a pair of gate contacts on the shallow n-type implants and the aluminum well therebetween, on the drain regions, and on the pair of gate insulating regions, respectively. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30)
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31. A method of fabricating a silicon carbide vertical power MOSFET comprising the steps of:
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implanting a pair of spaced apart aluminum wells into a drift region at a surface of a silicon carbide substrate; masking the drift region at the surface of the silicon carbide substrate to define a first pair of openings on the drift region, between the pair of the aluminum wells; first implanting p-type dopants into the silicon carbide substrate through the first pair of openings at implantation energy and dosage that form deep p-type implants; then implanting n-type dopants into the silicon carbide substrate through the first pair of openings at implantation energy and dosage that form shallow n-type implants relative to the deep p-type implants; annealing at temperature and time that is sufficient to laterally diffuse the respective deep p-type implants to the surface of the silicon carbide substrate surrounding the respective shallow n-type implants, without vertically diffusing the respective deep p-type implants to the surface of the silicon carbide substrate through the respective shallow n-type implants, to thereby form a pair of channel regions in the laterally diffused p-type implants at the surface of the silicon carbide substrate, between the shallow n-type implants; forming a gate insulating region at the surface of the silicon carbide substrate extending on and between the pair of channel regions; forming a pair of source contacts, a gate contact and a drain contact on the respective shallow n-type implants and extending on the aluminum well adjacent thereto, on the gate insulating region, and on a second face of the silicon carbide substrate opposite the drift region, respectively. - View Dependent Claims (32, 33, 34, 35, 36, 37)
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38. A method of fabricating a silicon carbide vertical power MOSFET comprising the steps of:
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implanting a pair of spaced apart aluminum wells into a drift region at a surface of a silicon carbide substrate; masking the drift region at the surface of the silicon carbide substrate to define a first pair of openings on the drift region, between the pair of the aluminum wells; first implanting n-type dopants into the silicon carbide substrate through the first pair of openings at implantation energy and dosage that form shallow n-type implants; electrically activating the n-type dopants; then implanting p-type dopants into the silicon carbide substrate through the first pair of openings at implantation energy and dosage that form deep p-type implants relative to the shallow n-type implants; annealing at temperature and time that is sufficient to laterally diffuse the respective deep p-type implants to the surface of the silicon carbide substrate surrounding the respective shallow n-type implants, without vertically diffusing the respective deep p-type implants to the surface of the silicon carbide substrate through the respective shallow n-type implants, to thereby form a pair of channel regions in the laterally diffused p-type implants at the surface of the silicon carbide substrate, between the shallow n-type implants; forming a gate insulating region at the surface of the silicon carbide substrate extending one and between the pair of channel regions; forming a pair of source contacts, a gate contact and a drain contact on the respective shallow n-type implants and extending on the aluminum well adjacent thereto, on the gate insulating region, and on a second face of the silicon carbide substrate opposite the drift region, respectively. - View Dependent Claims (39, 40, 41, 42, 43, 44)
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Specification