Method for fabricating a semiconductor device

• US 6,107,148 A
• Filed: 10/26/1998
• Issued: 08/22/2000
• Est. Priority Date: 10/26/1998
• Status: Expired due to Fees

• Current Assignee: Nippon Steel Semiconductor Corporation (United Microelectronics Corporation)
• Original Assignee: Nippon Steel Semiconductor Corporation (United Microelectronics Corporation)
• Inventors: Taki, Masushi
• Primary Examiner(s): Trinh, Michael
• Application Number:
  US09/178,510
• Time in Patent Office: 666 Days
• Field of Search: 438/303, 438/305, 438/306, 438/307, 438/299, 438/595, 438/301, 438/585, 438/FOR 188, 438/673, 438/531, 148/DIG. 161
• US Class Current: 438/303
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method for fabricating a semiconductor device having LDD structure. The method includes: a first step for forming an electrically insulating layer on an active area defined on a surface of a semiconductor substrate; a second step for forming a conductive layer on said insulating layer; a third step for forming a patterned photoresist layer of a downward tapered shape on said conductive layer; a fourth step for forming a gate electrode by patterning said conductive layer using a mask provided by bottom portions of said patterned photoresist layer; a fifth step for forming heavilyly doped regions at both sides of said gate electrode by introducing ions using a mask provided by top portions of said patterned photoresist layer; a sixth step for removing said patterned photoresist layer; and a seventh step for forming lightly doped regions at both sides of said gate electrode by introducing ions using a mask provided by said gate electrode.

Claims

1. A method for fabricating a semiconductor device comprising:

a first step for forming an electrically insulating layer on an active area defined on a surface of a semiconductor substrate;

a second step for forming a conductive layer on said insulating layer;

a third step for forming a patterned photoresist layer of a downward tapered shape on said conductive layer;

a fourth step for forming a gate electrode by patterning said conductive layer using a mask provided by bottom portions of said patterned photoresist layer;

a fifth step for forming heavily doped regions at both sides of said gate electrode by introducing ions using a mask provided by top portions of said patterned photoresist layer;

a sixth step for removing said patterned photoresist layer; and

a seventh step for forming lightly doped regions at both sides of said gate electrode by introducing ions using a mask provided by said gate electrode.

2. The method of claim 1 wherein said patterned photoresist is formed by using a technique of image inversion.

3. The method of claim 1 wherein a cross link is performed during said third step for forming said patterned photoresist.

4. The method of claim 1 wherein said patterned photoresist comprises amine.

5. The method of claim 2 wherein said patterned photoresist comprises amine.

6. The method of claim 1 wherein said electrically insulating layer is patterned together with said underlying conductive layer in said fourth step.

7. The method of claim 2 wherein said electrically insulating layer is patterned together with said underlying conductive layer in said fourth step.

8. The method of claim 3 wherein said electrically insulating layer is patterned together with said underlying conductive layer in said fourth step.