Method of manufacturing a trench structure in a semiconductor substrate

• US 6,107,158 A
• Filed: 03/25/1998
• Issued: 08/22/2000
• Est. Priority Date: 01/16/1997
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Zheng, Jie, Monsees, Suzanne, Gabriel, Calvin Todd
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US09/047,959
• Time in Patent Office: 881 Days
• Field of Search: 438/424, 438/700, 438/701, 438/713, 438/719, 438/FOR 118, 438/FOR 227
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: Y10S 438/978 forming tapered edges on substrate or adjacent layers

Abstract

A shallow trench isolation structure and method for forming such structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall sloping inwardly towards the center of a substantially planar bottom surface, and a second sidewall sloping inwardly towards the center of the substantially planar bottom surface. Additionally, a cross section of the trench has a first rounded bottom trench corner at an interface of the first sidewall and the substantially planar bottom surface, and a second rounded bottom trench corner at an interface of the second sidewall and the substantially planar bottom surface. Furthermore, the trench of the present invention has a first rounded upper trench corner at the interface of the first sidewall and the top surface of the semiconductor substrate, and a second rounded upper trench corner at the interface of the second sidewall and the top surface of the semiconductor substrate. Thus, the trench of the present invention does not have micro-trenches formed into the bottom surface thereof. Additionally, the present invention does not have the sharp upper and bottom corners found in conventional trenches formed using a shallow trench isolation method. The present invention also provides a method to eliminate deleterious micromasking and spike formation.

Claims

1. A shallow trench isolation method for forming a trench in a semiconductor substrate which has been contacted with a fluorine containing gas comprising the steps of:

a) introducing a non-oxygen containing etchant into an etching environment, wherein step a) further comprises the steps of;

a1) introducing helium into said etching environment at a rate of approximately 100 standard cubic centimeters per minute;

a2) introducing chlorine into said etching environment at a rate of approximately 70 standard cubic centimeters per minute; and

a3) introducing hydrogen bromide into said etching environment at a rate of approximately 70 standard cubic centimeters per minute;

b) subsequently etching, within said etching environment, the semiconductor substrate;

c) subsequently introducing an oxygen containing etchant into said etching environment; and

d) subsequently etching, within said etching environment, said semiconductor substrate until a trench of a depth is formed into said semiconductor substrate until a cross-section of the trench formed into said semiconductor substrate has the following features;

a substantially planar bottom surface;

a first sidewall sloping inwardly towards the center of said substantially planar bottom surface;

.

a second sidewall sloping inwardly towards said center of said substantially planar bottom surface;

a first rounded bottom trench corner at an interface of said first sidewall and said substantially planar bottom surface;

a second rounded bottom trench corner at an interface of said second sidewall and said substantially planar bottom surface;

a first rounded upper trench corner at the interface of said first sidewall and the top surface of said semiconductor substrate; and

a second rounded upper trench corner at the interface of said second sidewall and said top surface of said semiconductor substrate.

2. The shallow trench isolation method as recited in claim 1 wherein step c) further comprises the steps of:

c1) introducing helium into said etching environment;

c2) introducing chlorine into said etching environment;

c3) introducing hydrogen bromide into said etching environment; and

c4) introducing oxygen bromide into said etching environment.

3. The shallow trench isolation method as recited in claim 2 wherein step c1) comprises the step of:

introducing helium into said etching environment at a rate of approximately 100 standard cubic centimeters per minute.

4. The shallow trench isolation method as recited in claim 2 wherein step c2) comprises the step of:

introducing chlorine into said etching environment at a rate of approximately 70 standard cubic centimeters per minute.

5. The shallow trench isolation method as recited in claim 2 wherein step c3) comprises the step of:

introducing hydrogen bromide into said etching environment at a rate of approximately 70 standard cubic centimeters per minute.

6. The shallow trench isolation method as recited in claim 2 wherein step c4) comprises the step of:

introducing oxygen into said etching environment at a rate of approximately 5 standard cubic centimeters per minute.

7. The shallow trench isolation method as recited in claim 1 wherein step a1) comprises the step of:

introducing helium into said etching environment such that said helium comprises in the range of 5-50 percent by volume of etchant gas.

8. The shallow trench isolation method as recited in claim 1 wherein step a2) comprises the step of:

introducing chlorine into said etching environment such that said chlorine comprises in the range of 10-90 percent by volume of etchant gas.

9. The shallow trench isolation method as recited in claim 2 wherein step c1) comprises the step of:

introducing helium into said etching environment such that said helium comprises in the range of 5-50 percent by volume of etchant gas.

10. The shallow trench isolation method as recited in claim 2 wherein step c2) comprises the step of:

introducing chlorine into said etching environment such that said chlorine comprises in the range of 10-90 percent by volume of etchant gas.

11. The shallow trench isolation method as recited in claim 2 wherein step c4) comprises the step of:

introducing oxygen into said etching environment such that said oxygen comprises in the range of 0.5-20 percent by volume of etchant gas.