MOSFET having buried shield plate for reduced gate/drain capacitance

• US 6,107,160 A
• Filed: 04/22/1998
• Issued: 08/22/2000
• Est. Priority Date: 08/04/1997
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Spectrian Corp. (REMEC, Inc.)
• Inventors: Ng, Daniel, Hebert, Francois
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Berezny, Neal
• Application Number:
  US09/064,709
• Time in Patent Office: 853 Days
• Field of Search: 438/454, 438/286, 438/283, 438/284, 438/183, 438/197, 257/340, 257/386
• US Class Current: 438/454
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Gate to drain capacitance in a lateral DMOS and vertical DMOS field effect transistor is minimized by providing a conductive shield plate under the gate and between the gate and the drain of the transistor. In operation, the shield plate is preferably connected to a DC voltage potential and coupled to AC ground for RF power applications. The shield plate is readily fabricated in a conventional polysilicon gate process by adding one additional polysilicon deposition (or other suitable material), one additional mask, and one additional etch step. The shield plate can include a raised portion which provides lateral capacitive isolation between the gate and the drain. Alternatively, a shield contact can be provided above the shield plate and between the gate and drain to provide lateral isolation.

Claims

1. A method of fabricating a lateral RF field effect transistor with a shield plate between a gate and a drain of the transistor comprising the steps of:

a) providing a semiconductor substrate having a major surface,

b) forming an oxide layer over the major surface,

c) depositing a doped polysilicon layer on the oxide layer,

d) selectively etching the doped polysilicon layer to form a shield plate,

e) oxidizing exposed surfaces of the shield plate,

f) forming spaced source and drain regions in said major surface with a channel therebetween, said shield plate being adjacent to the channel, and

g) forming a gate over the channel and overlying at least part of the shield plate.

2. The method of claim 1 and further including forming a doped well structure in the major surface extending from the shield plate to the drain.

3. The method of claim 1 wherein step b) includes forming a bump oxide whereby steps c) and d) form a doped polysilicon layer having a raised portion to provide lateral shielding between the gate and the drain.

4. The method of claim 1 and further including the steps of forming electrodes to the source, the drain, the gate, and the shield plate.

5. The method of claim 4 wherein the steps of forming electrodes form a source electrode overlying at least part of the gate.

6. The method of claim 5 wherein the source electrode extends into contact with the shield plate.

7. The method of claim 4 wherein said electrodes include silicide layers on contact surfaces.