Insulated gate semiconductor device and manufacturing method thereof

• US 6,107,650 A
• Filed: 02/14/1995
• Issued: 08/22/2000
• Est. Priority Date: 02/21/1994
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki, Minato, Tadaharu, Harada, Masana, Nishihara, Hidenori
• Primary Examiner(s): HARDY, DAVID B
• Application Number:
  US08/388,599
• Time in Patent Office: 2,016 Days
• Field of Search: 257/124, 257/125, 257/127, 257/139, 257/141, 257/153, 257/170, 257/172, 257/173, 257/174, 257/175, 257/176, 257/283, 257/329, 257/330, 257/331, 257/332, 257/333, 257/334 , 257/337, 257/341
• US Class Current: 257/139
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48139 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4847 the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49431 on the semiconductor or solid-state body
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01088 : Radium [Ra]
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An insulated gate semiconductor device in which the ON voltage is decreased by providing strip like trenches (207) having gate electrodes (210) buried therein are formed in an upper main surface of a semiconductor base body (200), and an N⁺ emitter layer (206) is exposed in a ladder-like form in the upper main surface of the semiconductor base body interposed between adjacent trenches (207). Accordingly, even if the position of a zonal region (Ra) which is a contact surface with an emitter electrode (212) is shifted, the emitter electrode (212) is surely in contact with the N⁺ emitter layer (206). Furthermore, the ladder-like N⁺ emitter layer (206) is formed adjacent to the trench (207), so that a channel region (208) is formed without discontinuation along the trench (207). Accordingly, it has the effect of facilitating miniaturization of elements and of effectively making use of the miniaturization to decrease the ON voltage.

Claims

1. An insulated gate semiconductor device, comprising:

a semiconductor base body having an upper main surface and a lower main surface,

the semiconductor base body comprising,

a first semiconductor layer of a first conductivity type,

a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and

a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer,

said semiconductor base body having a plurality of trenches arranged substantially in a stripe form along said upper main surface and formed from said upper main surface to said first semiconductor layer,

said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween,

said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches,

said insulated gate semiconductor device further comprising,

a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode,

a second main electrode electrically connected to said lower main surface, and

a conductive layer having platinum silicide and interposed between said first main electrode and said upper main surface,

said first main electrode and said second and third semiconductor layers being electrically connected through the conductive layer; and

a thickness of said second semiconductor layer and shape of said plurality of trenches are set so that a boundary of said first semiconductor layer and said second semiconductor layer is located below an intersection of a plane including an opening end of said trench in said upper main surface and inclined by an inclination angle of 45°

with respect to said upper main surface and a wall surface of said trench adjacent to that trench.

2. The insulated gate semiconductor device according to claim 1, wherein a contact surface between said first main electrode and said second semiconductor layer and a contact surface between said first main electrode and said third semiconductor layer are both rectangular, and width of one side of said contact surfaces is in a range of 0.5 μ

m to 3 μ

m.

3. An insulated gate semiconductor device, comprising:

a semiconductor base body having an upper main surface and a lower main surface,

the semiconductor base body comprising,

a first semiconductor layer of a first conductivity type,

a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and

a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer,

said semiconductor base body having a plurality of trenches arranged substantially in a stripe form along said upper main surface and formed from said upper main surface to said first semiconductor layer,

said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween,

said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches, and

a thickness of said second semiconductor layer and shape of said plurality of trenches are set so that a boundary of said first semiconductor layer and said second semiconductor layer is located below an intersection of a plane including an opening end of said trench in said upper main surface and inclined by an inclination angle of 45°

with respect to said upper main surface and a wall surface of said trench adjacent to that trench,

said insulated gate semiconductor device further comprising,

a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode, and

a second main electrode electrically connected to said lower main surface, and

shape of said third semiconductor layer being set so that a maximum distance Lmax defined as a distance to a point which is farthest from an exposure surface of said second semiconductor layer in said upper main surface among points on an intersection of a boundary plane of said third semiconductor layer and said second semiconductor layer and said trench is given by Vpn>

Jpr×

ρ

_pn ×

Lmax for built-in potential Vpn peculiar to a junction portion of said second semiconductor layer and said third semiconductor layer, density Jpr of current flowing in said second semiconductor layer right under said third semiconductor layer when main current with magnitude corresponding to rated current of said insulated gate semiconductor device is caused to flow between said first main electrode and said second main electrode, and resistivity ρ

_pn of said second semiconductor layer right under said third semiconductor layer.

4. An insulated gate semiconductor device, comprising:

a semiconductor base body having an upper main surface and a lower main surface,

the semiconductor base body comprising,

a first semiconductor layer of a first conductivity type,

a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and

a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer,

said semiconductor base body having a plurality of trenches arranged substantially in a stripe form along said upper main surface and formed from said upper main surface to said first semiconductor layer,

said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween,

said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches, and

a thickness of said second semiconductor layer and shape of said plurality of trenches are set so that a boundary of said first semiconductor layer and said second semiconductor layer is located below an intersection of a plane including an opening end of said trench in said upper main surface and inclined by an inclination angle of 45°

with respect to said upper main surface and a wall surface of said trench adjacent to that trench,

said insulated gate semiconductor device further comprising,

a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode, and

a second main electrode electrically connected to said lower main surface, and

shape of said third semiconductor layer being set so that a maximum distance Lmax defined as a distance to a point which is farthest from an exposure surface of said second semiconductor layer in said upper main surface among points on an intersection of a boundary plane of said third semiconductor layer and said second semiconductor layer and said trench is given by Vpn>

n×

Jpr×

ρ

_pn ×

Lmax for built-in potential Vpn peculiar to a junction portion of said second semiconductor layer and said third semiconductor layer, density Jpr of current flowing in said second semiconductor layer right under said third semiconductor layer when main current with magnitude corresponding to rated current of said insulated gate semiconductor device is caused to flow between said first main electrode and said second main electrode, a ratio n of a magnitude of the main current when short-circuited load is connected between said first main electrode and second main electrode and said rated current, and resistivity ρ

_pn of said second semiconductor layer right under said third semiconductor layer.

5. An insulated gate semiconductor device, comprising

a semiconductor base body having an upper main surface and a lower main surface,

the semiconductor base body comprising,

a first semiconductor layer of a first conductivity type,

a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and

a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer,

said semiconductor base body having a plurality of trenches arranged substantially in a stripe form along said upper main surface and formed from said upper main surface to said first semiconductor layer,

said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween,

said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches,

said insulated gate semiconductor device further comprising,

a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode,

a second main electrode electrically connected to said lower main surface, and

overcurrent protection means for limiting the magnitude of main current flowing between said first main electrode and said second main electrode so as not to exceed a predetermined limit current value, and

shape of said third semiconductor layer being set so that a maximum distance Lmax defined as a distance to a point which is farthest from an exposure surface of said second semiconductor layer in said upper main surface among points on an intersection of a boundary plane of said third semiconductor layer and said second semiconductor layer and said trench is given by Vpn>

m×

Jpr×

ρ

_pn ×

Lmax for built-in potential Vpn peculiar to a junction portion of said second semiconductor layer and said third semiconductor layer, density Jpr of current flowing in said second semiconductor layer right under said third semiconductor layer when main current with magnitude corresponding to rated current of the device is passed between said first main electrode and said second main electrode, a ratio m of said predetermined limit current value and said rated current, and resistivity ρ

_pn of said second semiconductor layer right under said third semiconductor layer.

6. An insulated gate semiconductor device, comprising

a semiconductor base body having an upper main surface and a lower main surface,

the semiconductor base body comprising,

a first semiconductor layer of a first conductivity type,

a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and

a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer,

said semiconductor base body having a plurality of trenches arranged substantially in a stripe form along said upper main surface and formed from said upper main surface to said first semiconductor layer,

said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween,

said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches,

said insulated gate semiconductor device further comprising,

a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode,

a second main electrode electrically connected to said lower main surface,

said semiconductor base body being single crystal and said upper main surface of said semiconductor base body is along a <

100>

crystal plane, and

a thickness of said second semiconductor layer and shape of said plurality of trenches are set so that a boundary of said first semiconductor layer and said second semiconductor layer is located below an intersection of a plane including an opening end of said trench in said upper main surface and inclined by an inclination angle of 45°

with respect to said upper main surface and a wall surface of said trench adjacent to that trench.

7. An insulated gate semiconductor device in which a plurality of insulated gate semiconductor elements having trench•

gate and having the same structure are arranged substantially in a stripe form at equal intervals in a semiconductor base body along its main structure, comprising,

a main electrode connected to said plurality of insulated gate semiconductor elements at said main surface of said semiconductor base body,

an external electrode provided outside said semiconductor base body for making an electric connection between said insulated gate semiconductor device and an external device,

a plurality of interconnections each having one end connected to said main electrode and another end connected to said external electrode to electrically connect the main electrode and the external electrode, and

said plurality of interconnections being connected to respective of a plurality of unit regions defined by nearly equally dividing a region occupied by said plurality of insulated gate semiconductor elements in said main surface so that there is substantially an equal number of interconnections per unit region.

8. The insulated gate semiconductor device according to claim 7, wherein an area of said unit region is in the range of 2 mm² to 4 mm².

10. The insulated gate semiconductor device according to claim 7, wherein said plurality of interconnections are emitter wires each have one end connected to a main emitter electrode and another end connected to an external emitter electrode.

9. An insulated gate semiconductor device, comprising,

a semiconductor base body having a main surface,

the semiconductor base body having a plurality of insulated gate semiconductor elements,

the plurality of insulated gate semiconductor elements having trench gate formed in said main surface and being arranged in a substantially linear stripe from along said main surface, and

said insulated gate semiconductor device having,

a main electrode connected to said main surface of said semiconductor base body,

an external electrode provided outside said semiconductor base body to make an electric connection between said insulated gate semiconductor device and an external device, and

an interconnection having its one end connected to said main electrode and the other end connected to said external electrode to electrically connect the main electrode and the external electrode, wherein

said interconnection is connected to said main electrode so that an angle formed by an orthogonal projection of said interconnection on the main surface with a direction of said insulated gate semiconductor element is in the range of 30°

to 150°

.

11. The insulated gate semiconductor device according to claim 9, wherein said interconnection comprises an emitter wire having one end connected to a main emitter electrode and another end connected to an external emitter electrode.

12. An insulated gate semiconductor device, comprising:

a semiconductor base body having an upper main surface and a lower main surface,

the semiconductor base body comprising,

a first semiconductor layer of a first conductivity type,

a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and

a third semiconductor layer of the first conductivity type selectively formed in an upper surface portion of the second semiconductor layer,

said semiconductor base body having a plurality of trenches arranged substantially in a stripe form along said upper main surface and formed from said upper main surface to said first semiconductor layer,

said trench having a gate insulating film formed covering its inner wall and a gate electrode buried in said trench with the gate insulating film interposed therebetween,

said second semiconductor layer and said third semiconductor layer being selectively exposed in said upper main surface interposed between adjacent said trenches, and

a thickness of said second semiconductor layer and shape of said plurality of trenches are set so that a boundary of said first semiconductor layer and said second semiconductor layer is located below an intersection of a plane including an opening end of said trench in said upper main surface and inclined by an inclination angle of 45°

with respect to said upper main surface and a wall surface of said trench adjacent to that trench,

said insulated gate semiconductor device further comprising,

a first main electrode electrically connected to both of said second and third semiconductor layers on said upper main surface and insulated from said gate electrode, and

a second main electrode electrically connected to said lower main surface, and

overcurrent protection means for limiting the magnitude of main current flowing between said first main electrode and said second main electrode so as not to exceed a predetermined limit current value, and

shape of said third semiconductor layer being set so that a maximum distance Lmax defined as a distance to a point which is farthest from an exposure surface of said second semiconductor layer in said upper main surface among points on an intersection of a boundary plane of said third semiconductor layer and said second semiconductor layer and said trench is given by Vpn>

m×

Jpr×

ρ

_pn ×

Lmax for built-in potential Vpn peculiar to a junction portion of said second semiconductor layer and said third semiconductor layer, density Jpr of current flowing in said second semiconductor layer right under said third semiconductor layer when main current with magnitude corresponding to rated current of the device is passed between said first main electrode and said second main electrode, a ratio m of said predetermined limit current value and said rated current, and resistivity ρ

_pn of said second semiconductor layer right under said third semiconductor layer.