Ferroelectric transistors, semiconductor storage devices, method of operating ferroelectric transistors and method of manufacturing ferromagnetic transistors

• US 6,107,656 A
• Filed: 10/28/1997
• Issued: 08/22/2000
• Est. Priority Date: 06/06/1997
• Status: Expired due to Fees

• Current Assignee: OKI Electric Industry Company Limited
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Igarashi, Yasushi
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): Eckert, II, George C.
• Application Number:
  US08/958,989
• Time in Patent Office: 1,029 Days
• Field of Search: 257/295, 257/316, 365/145
• US Class Current: 257/295
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/6684 with a ferroelectric gate insulator
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H10B 51/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
• CPC Class Codes: H10B 51/30 characterised by the memory core region
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

A method of manufacturing a ferroelectric transistor is provided by which the characteristic of the transistor is not degraded because of a heated process. The ferroelectric transistor has a gate unit on the underlying structure. The gate unit includes a gate electrode, a ferroelectric film and a gate insulation film deposited on one another in this order. A channel layer is provided on the gate insulation film. A first main electrode and a second main electrode are provided in a spaced apart manner on the channel layer. The channel layer is used as a channel in operating the transistor. Thus, the carrier density of the channel is controlled by using the spontaneous polarization of the ferroelectric film.

Claims

1. A ferroelectric transistor comprising:

a gate unit including

an underlying layer,

a gate electrode deposited on said underlying layer,

a gate insulation film,

a ferroelectric film, and

an upper conductive layer between said gate insulation film and said ferroelectric film,

wherein said gate electrode, said ferroelectric film, and said gate insulation film are deposited in order on said underlying layer;

a channel layer deposited on said gate insulation film of said gate unit operable to control a carrier density by spontaneous polarization of said ferroelectric film; and

first and second main electrodes spaced apart from each other on said channel layer.

2. A ferroelectric transistor as claimed in claim 1, wherein said gate unit includes a lower conductive layer between said ferroelectric film and said gate electrode.

3. A ferroelectric transistor as claimed in claim 2, wherein said lower conductive layer is formed of any one material or any combination of more than one material selected from among IrO₂, Ir, Ru, Pt, RuO₂, SrRuO₃, La_1-x Sr_x CoO₃₁ wherein x is a positive integer, and SrMoO₃.

4. A ferroelectric transistor as claimed in claim 1, wherein:

said gate unit includes a metal oxide layer between said channel layer and said gate insulation layer; and

said metal oxide layer is formed of a material having a heat of oxide formation which is smaller than a heat of oxide formation of said channel layer.

5. A ferroelectric transistor as claimed in claim 4, wherein said metal oxide layer is formed of any one material or any combination of more than one material selected from among ZrO₂ l TiO₂, HfO₂, and Al₂ O₃.

6. A ferroelectric transistor as claimed in claim 1, wherein said upper conductive layer is formed of any one material or any combination of more than one material selected from among IrO₂, Ir, Ru, Pt, RuO₂, SrRuO₃, La_1-x Sr_x CoO₃, wherein x is a positive integer, and SrMoO₃.

7. A ferroelectric transistor as claimed in claim 1, wherein said first and second main electrodes are formed of polysilicon or amorphous silicon.

8. A ferroelectric transistor as claimed in claim 1, wherein said first and second main electrodes are formed as regions doped with impurities on said channel layer.

9. A ferroelectric transistor as claimed in claim 1, wherein said gate electrode is formed of any one material selected from among W, Ta, Mo, TiN, Nb, V, TaN, TaSiN, TiW, TiWN, and TiAlN.

10. A ferroelectric transistor comprising:

a gate unit including

an underlying layer,

a gate electrode deposited on said underlying layer,

a gate insulation film,

a ferroelectric film, and

an upper conductive layer between said gate insulation film and said ferroelectric film,

wherein said gate electrode, said ferroelectric film, and said gate insulation film are deposited in order on said underlying layer;

a channel layer deposited on said gate insulation film of said gate unit operable to control a carrier density by spontaneous polarization of said ferroelectric film; and

first and second main electrodes spaced apart from each other on said channel layer, wherein an area of said channel layer which contacts said first main electrode is different than an area of said channel layer which contacts said second main electrode.

11. A ferroelectric transistor as claimed in claim 10, wherein said gate unit includes a lower conductive layer between said ferroelectric film and said gate electrode.

12. A ferroelectric transistor as claimed in claim 11, wherein said lower conductive layer is formed of any one material or any combination of more than one material selected from among IrO₂, Ir, Ru, Pt, RuO₂, SrRuO₃, La_1-x Sr_x CoO₃, wherein x is a positive integer, and SrMoO₃.

13. A ferroelectric transistor as claimed in claim 10, wherein:

said gate unit includes a metal oxide layer between said channel layer and said gate insulation layer; and

said metal oxide layer is formed of a material having a heat of oxide formation which is smaller than a heat of oxide formation of said channel layer.

14. A ferroelectric transistor as claimed in claim 13, wherein said metal oxide layer is formed of any one material or any combination of more than one material selected from among ZrO₂, TiO₂, HfO₂, and Al₂ O₃.

15. A ferroelectric transistor as claimed in claim 10, wherein said upper conductive layer is formed of any one material or any combination of more than one material selected from among IrO₂, Ir, Ru, Pt, RuO₂, SrRuO₃, La_1-x Sr_x CoO₃, wherein x is a positive integer, and SrMoO₃.

16. A ferroelectric transistor as claimed in claim 10, wherein said first and second main electrodes are formed of polysilicon or amorphous silicon.

17. A ferroelectric transistor as claimed in claim 10, wherein said first and second main electrodes are formed as regions doped with impurities on said channel layer.

18. A ferroelectric transistor as claimed in claim 10, wherein said gate electrode is formed of any one material selected from among W, Ta, Mo, TiN, Nb, V, TaN, TaSiN, TiW, TiWN, and TiAlN.