Vertical thin film transistor

• US 6,107,660 A
• Filed: 05/19/1999
• Issued: 08/22/2000
• Est. Priority Date: 05/19/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Worldwide Semiconductor Manufacturing Corp. (Taiwan Semiconductor Manufacturing Company Limited)
• Inventors: Liu, Chia-Chen, Yang, Ching-Nan
• Primary Examiner(s): HARDY, DAVID B
• Application Number:
  US09/314,623
• Time in Patent Office: 461 Days
• Field of Search: 257/329, 257/330, 257/393
• US Class Current: 257/329
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

The method includes forming a first polysilicon on a substrate. Subsequently, a first dielectric layer is formed on the first polysilicon. A second polysilicon is pattern on the first dielectric layer, followed by depositing a second dielectric layer formed thereon. An etching is performed to etch the second dielectric layer, the second polysilicon layer through the first dielectric layer for generating an opening. An oxide layer is formed on the side-wall of the opening. A doped polysilicon layer is located at the lower portion of the opening. An undoped polysilicon layer is deposited on the second dielectric layer and refilled into the opening. An etching back is carried out to remove the layer over the second dielectric layer. A third polysilicon is patterned on the surface of the second dielectric layer. An isolation layer is deposited over the feature. A plurality of contact holes are generated in those isolation layers.

Claims

1. A vertical thin film transistor formed on a substrate, the vertical thin film transistor comprising:

a conductive pad formed on said substrate;

a first isolation layer formed on said conductive pad and said substrate;

a gate patterned on said first isolation layer, wherein said gate is partially overlap with said conductive pad;

a second isolation layer formed on said first isolation layer and said gate, wherein said second isolation layer, said first isolation layer and said gate includes an opening through therein;

a gate oxide formed on a side-wall of said opening;

a first doped region located at a lower portion of said opening;

an undoped polysilicon formed in said opening and on said first doped region;

a conductive structure formed on said opening and contacting said undoped polysilicon to act as a second doped region; and

a third isolation layer formed on said conductive structure and said second isolation layer;

wherein

said first, second and third isolation layers includes a first contact hole through therein, said

second and said third isolation layers including a second contact hole through therein, said

third isolation layer including a third opening through therein.

2. The vertical thin film transistor of claim 1, wherein said first isolation layer comprises oxide.

3. The vertical thin film transistor of claim 1, wherein said second isolation layer comprises oxide.

4. The vertical thin film transistor of claim 1, wherein said third isolation layer comprises oxide.

5. The vertical thin film transistor of claim 1, wherein a concentration of dopants of said conductive pad is about 1E20 to 3E20 atoms/cm³.

6. The vertical thin film transistor of claim 1, wherein a concentration of dopants of said gate is about 1E20 to 3E20 atoms/cm³.

7. The vertical thin film transistor of claim 1, wherein a concentration of dopants of said conductive structure is about 1E20 to 3E20 atoms/cm³.

8. The vertical thin film transistor of claim 1, wherein said first doped region comprises polysilicon.

9. The vertical thin film transistor of claim 1, wherein said second doped region comprises polysilicon.