Interconnect structure for FPGA with configurable delay locked loop
First Claim
1. A field programmable gate array (FPGA), comprising:
- a first pad;
a first delay locked loop;
a first global clock driver;
general interconnect circuitry; and
programmable connections selectively connecting the first pad to the first delay locked loop, the first global clock driver, and the general interconnect circuitry.
1 Assignment
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Accused Products
Abstract
A field programmable gate array (FPGA) is provided that includes a plurality of pads and a plurality of delay locked loops (DLLs). Programmable connections enable any one of the DLLs to have multiple pads as inputs. Programmable connections also enable the DLLs to be selectively connected to one another. Programmable connections further enable the pads to be selectively connected to general interconnect circuitry or global clock drivers of the FPGA. Programmable connections are also provided for selectively connecting the DLLs to the global clock drivers. This FPGA structure enables the pads to be configured to receive either clock or non-clock signals. This structure also enables the FPGA to operate as a clock mirror, and to generate one clock signal from another clock signal on the FPGA.
96 Citations
19 Claims
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1. A field programmable gate array (FPGA), comprising:
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a first pad; a first delay locked loop; a first global clock driver; general interconnect circuitry; and programmable connections selectively connecting the first pad to the first delay locked loop, the first global clock driver, and the general interconnect circuitry. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A field programmable gate array (FPGA), comprising:
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a first pad; a first delay locked loop; a first trace extending between the first pad and the first delay locked loop, the first trace exhibiting a first delay; a global clock routing network for receiving and distributing an input clock signal; and a second trace extending between the global clock routing network and the first delay locked loop, the second trace exhibiting a second delay, wherein the first delay is equal to the second delay. - View Dependent Claims (14, 15, 16)
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17. A method of operating a field programmable gate array (FPGA) comprising the steps of:
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routing a reference clock signal from a first pad to a first delay locked loop on the FPGA; generating a first output clock signal with the first delay locked loop; transmitting the first output clock signal off of the FPGA; receiving the first output clock signal on a second pad of the FPGA; routing the first output clock signal from the second pad to the first delay locked loop as a feedback clock signal; and introducing a delay to the first output clock signal with the first delay locked loop, the delay being selected such that the first output clock signal on the second pad matches the reference clock signal on the first pad. - View Dependent Claims (18)
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19. A method of operating a field programmable gate array (FPGA), the method comprising the steps of:
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routing a reference clock signal from a first pad to a first delay locked loop on the FPGA; generating a first output clock signal with the first delay locked loop; routing the first output clock signal from the first delay locked loop to a second delay locked loop on the FPGA; and generating a second output clock signal with the second delay locked loop.
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Specification