Interconnect structure for FPGA with configurable delay locked loop

• US 6,107,826 A
• Filed: 08/19/1998
• Issued: 08/22/2000
• Est. Priority Date: 08/19/1998
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Young, Steven P., Bauer, Trevor J.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/136,461
• Time in Patent Office: 734 Days
• Field of Search: 326/38, 326/39, 326/40, 326/41, 326/47, 326/101
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset

Abstract

A field programmable gate array (FPGA) is provided that includes a plurality of pads and a plurality of delay locked loops (DLLs). Programmable connections enable any one of the DLLs to have multiple pads as inputs. Programmable connections also enable the DLLs to be selectively connected to one another. Programmable connections further enable the pads to be selectively connected to general interconnect circuitry or global clock drivers of the FPGA. Programmable connections are also provided for selectively connecting the DLLs to the global clock drivers. This FPGA structure enables the pads to be configured to receive either clock or non-clock signals. This structure also enables the FPGA to operate as a clock mirror, and to generate one clock signal from another clock signal on the FPGA.

Claims

1. A field programmable gate array (FPGA), comprising:

a first pad;

a first delay locked loop;

a first global clock driver;

general interconnect circuitry; and

programmable connections selectively connecting the first pad to the first delay locked loop, the first global clock driver, and the general interconnect circuitry.

2. The FPGA of claim 1, further comprising:

a second pad; and

a second delay locked loop;

wherein the programmable connections further selectively connect the second pad to the first delay locked loop, the second delay locked loop, the first global clock driver, and the general interconnect circuitry.

3. The FPGA of claim 2, wherein the programmable connections further selectively connect the first pad to the second delay locked loop.

4. The FPGA of claim 1, further comprising an array of configurable logic blocks (CLBs), wherein the general interconnect circuitry comprises horizontal long lines extending along the array of CLBs along a first axis, and vertical long lines extending along the array of CLBs along a second axis.

5. The FPGA of claim 4, wherein the general interconnect circuitry further comprises hex lines, each of the hex lines extending across six gaps between adjacent CLBs.

6. The FPGA of claim 2, wherein the first and second delay locked loops each comprise a clock input terminal and a feedback input terminal, and wherein the programmable connections comprise programmable connections located between the first and second pads and the clock input terminals, and programmable connections located between the first and second pads and the feedback input terminals.

7. The FPGA of claim 2, further comprising programmable connections located between one or more output terminals of the first delay locked loop and an input terminal of the second delay locked loop.

8. The FPGA of claim 2, wherein the first and second pads are centrally located along an edge of the FPGA, and the first and second delay locked loops are located at opposite ends of the edge.

9. The FPGA of claim 2, further comprising a second global clock driver, and wherein the programmable connections further selectively connect at least one of the first pad and the second pad to the first global clock driver and the second global clock driver.

10. The FPGA of claim 9, wherein the programmable connections further selectively connect at least one of the first delay locked loop and the second delay locked loop to the first global clock driver and the second global clock driver.

11. The FPGA of claim 9, further comprising a global clock routing network connected to the first and second clock drivers, the global clock routing network being formed to distribute clock signals throughout the FPGA.

12. The FPGA of claim 11, wherein:

the first delay locked loop has a first feedback input terminal;

the second delay locked loop has a second feedback input terminal; and

the programmable connections further selectively connect the global clock routing network and the first and second feedback input terminals.

13. A field programmable gate array (FPGA), comprising:

a first pad;

a first delay locked loop;

a first trace extending between the first pad and the first delay locked loop, the first trace exhibiting a first delay;

a global clock routing network for receiving and distributing an input clock signal; and

a second trace extending between the global clock routing network and the first delay locked loop, the second trace exhibiting a second delay, wherein the first delay is equal to the second delay.

14. The FPGA of claim 13, wherein the first pad is located near a mid-point of an edge of the FPGA, and the first delay locked loop is located near an end of the edge.

15. The FPGA of claim 14, wherein the first trace extends between the mid-point and the end of the edge, and wherein the second trace extends from the end of the edge half way toward the mid-point and then extends back to the end of the edge.

16. The FPGA of claim 13, further comprising an adjustable delay circuit connected in series with the second trace.

17. A method of operating a field programmable gate array (FPGA) comprising the steps of:

routing a reference clock signal from a first pad to a first delay locked loop on the FPGA;

generating a first output clock signal with the first delay locked loop;

transmitting the first output clock signal off of the FPGA;

receiving the first output clock signal on a second pad of the FPGA;

routing the first output clock signal from the second pad to the first delay locked loop as a feedback clock signal; and

introducing a delay to the first output clock signal with the first delay locked loop, the delay being selected such that the first output clock signal on the second pad matches the reference clock signal on the first pad.

18. The method of claim 17, further comprising the steps of:

routing the first output clock signal from the second pad to a second delay locked loop on the FPGA; and

generating a second output clock signal in response to the first output clock signal with the second delay locked loop.

19. A method of operating a field programmable gate array (FPGA), the method comprising the steps of:

routing a reference clock signal from a first pad to a first delay locked loop on the FPGA;

generating a first output clock signal with the first delay locked loop;

routing the first output clock signal from the first delay locked loop to a second delay locked loop on the FPGA; and

generating a second output clock signal with the second delay locked loop.