Semiconductor integrated circuit

• US 6,107,869 A
• Filed: 06/11/1998
• Issued: 08/22/2000
• Est. Priority Date: 06/20/1997
• Status: Expired due to Term

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Hitachi Device Engineering Co., Ltd. (Hitachi, Ltd.), Hitachi, Ltd.
• Inventors: Akiba, Takesada, Kajigaya, Kazuhiko, Horiguchi, Masashi, Nakagome, Yoshinobu, Kawase, Yasushi
• Primary Examiner(s): KIM, JUNG H
• Application Number:
  US09/096,456
• Time in Patent Office: 803 Days
• Field of Search: 327/544, 327/564, 327/565, 327/566, 361/601, 361/605, 361/628, 361/631
• US Class Current: 327/544
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.

Claims

1. A semiconductor integrated circuit comprising:

a plurality of MOS logic circuits formed in a rectangular region over a semiconductor substrate;

a main power supply line provided along a long side of the rectangular region at a peripheral part of the rectangular region;

a plurality of sub-power lines arranged in a direction perpendicular to said main power supply line in the rectangular region; and

a plurality of switching MOS transistors for respectively connecting said sub-power supply lines to said main power supply line,

wherein said switching MOS transistors are kept off in an operation stop state of said MOS logic circuits connected to said sub-power supply lines,

wherein said switching MOS transistors are kept on in an operable state of said MOS logic circuits connected to said sub-power supply lines, and

wherein said switching MOS transistors are so arranged as to be covered with said main power supply line.

2. A semiconductor integrated circuit according to claim 1,

wherein said main power supply line includes a first main power supply line to which a first power supply voltage is supplied and a second main power supply line to which a second power supply voltage having a level lower than that of the first power supply voltage is supplied,

wherein a predetermined MOS logic circuit among said MOS logic circuits includes a p-channel MOS transistor, and

wherein a predetermined sub-power supply line connected to the source of said p-channel MOS transistor is connected to said first main power supply line through a corresponding switching MOS transistor.

3. A semiconductor integrated circuit according to claim 2,

wherein a predetermined MOS logic circuit among said MOS logic circuits includes an n-channel MOS transistor, and

wherein a predetermined sub-power supply line connected to the source of said n-channel MOS transistor is connected to said second main power supply line through a corresponding switching MOS transistor.

4. A semiconductor integrated circuit comprising:

a main power supply line extending in a first direction;

a plurality of sub-power supply lines extending in a second direction perpendicular to said first direction; and

switching MOS transistors for respectively connecting said sub-power supply lines to said main power supply line,

wherein said switching MOS transistors are so arranged as to be covered with said main power supply line,

wherein said switching MOS transistors are kept off in an operation stop state of said MOS logic circuits, and

wherein said switching MOS transistors are kept on in an operable state of said MOS logic circuits to which electric power is supplied through said sub-power supply lines.

5. A semiconductor integrated circuit comprising:

a plurality of MOS logic circuits formed over a semiconductor substrate;

a plurality of first sub-power supply lines extending in a first direction;

a plurality of second sub-power supply lines, each connected at intersection portions to said first sub-power supply lines, said second sub-power supply lines extending in a second direction crossing to said first direction;

a main power supply line extending in said second direction; and

a plurality of first switching MOS transistors for connecting said first sub-power supply lines to said main power supply line extending in said second direction,

wherein said first switching MOS transistors are kept off in an operation stop state of said MOS logic circuits,

wherein said first switching MOS transistors are kept on in an operable state of said MOS logic circuits, and

wherein said first switching MOS transistors are so arranged as to be covered with said main power supply line extending in said second direction.

6. A semiconductor integrated circuit according to claim 5, further comprising:

another main power supply line; and

a plurality of second switching MOS transistors for connecting said second sub-power supply lines to said another main power supply line,

wherein said second switching MOS transistors are kept off in an operation stop state of said MOS logic circuits and kept on in an operable state of said MOS logic circuits.

7. A semiconductor integrated circuit according to claim 6,

wherein said second switching MOS transistors are so arranged as to be covered with said another main power supply line.

8. A semiconductor integrated circuit according to claim 5,

wherein said main power supply line extending in said second direction includes a first main power supply line to which a first power supply voltage is supplied and a second main power supply line to which a second power supply voltage having a level lower than that of said first power supply voltage is supplied,

wherein a predetermined MOS logic circuit among said MOS logic circuits includes a p-channel MOS transistor, and

wherein the source of said p-channel MOS transistor is connected to said first main power supply line through a corresponding first switching MOS transistor.

9. A semiconductor integrated circuit according to claim 8,

wherein a predetermined MOS logic circuit among said MOS logic circuits includes an N-channel MOS transistor, and

wherein the source of said n-channel MOS transistor is connected to said second main power supply line through a corresponding first switching MOS transistor.

10. A semiconductor integrated circuit according to claim 6,

wherein said main power supply line extending in said second direction includes a first main power supply line to which a first power supply voltage is supplied and a second main power supply line to which a second power supply voltage having a level lower than that of said first power supply line is supplied,

wherein said another main power supply line includes a third main power supply line to which the first power supply voltage is supplied and a fourth main power supply line to which the second power supply voltage is supplied, and

wherein said MOS logic circuits each include a p-channel MOS transistor, the source of said p-channel MOS transistor being connected to said first main power supply line through a corresponding first switching MOS transistor, and the source of said p-channel MOS transistor being connected to said third main power supply line through a corresponding second switching MOS transistor.

11. A semiconductor integrated circuit according to claim 10,

wherein each of said MOS logic circuits includes an n-channel MOS transistor, the source of said n-channel MOS transistor being connected to said second main power supply line through a corresponding first switching MOS transistor, and the source of said n-channel MOS transistor being connected to said fourth main power supply line through a corresponding second switching MOS transistor.

12. A semiconductor integrated circuit comprising:

a plurality of memory mats including plural memory cells each having a selection terminal connected to a word line and being arranged like an array;

word drivers for selectively driving the word lines, regularly provided between said memory mats arranged like an array;

a plurality of MOS logic circuits for supplying a word-line driving voltage to said word drivers, regularly provided between said memory mats arranged like an array;

first sub-power supply lines, extending in a first direction, connected to power supply terminals of said MOS logic circuits,

second sub-power supply lines, extending in a second direction perpendicular to said first direction, said second sub-power supply lines being connected to said first sub-power supply lines at intersection portions thereof;

a main power supply line extending in said second direction; and

a plurality of switching MOS transistors for connecting said power supply terminals to said main power supply line,

wherein said switching MOS transistors are kept off in a standby state of said MOS logic circuits and kept on in an operable state of the MOS logic circuits, and

wherein said switching MOS transistors are so arranged as to be covered with said main power supply line.

13. A semiconductor integrated circuit according to claim 12,

wherein a selection signal is supplied to a group of word drivers from a common main word line, and said MOS logic circuits supply a word line driving level of said sub-power supply lines to said word drivers in accordance with a decoding signal for selecting one of said word drivers, and

wherein said sub-power supply lines are formed over the same wiring layer as the main word line.

14. A semiconductor integrated circuit according to claim 12, wherein a boosted voltage is supplied to said main power supply and the well region of a p-channel MOS transistor provided in said MOS logic circuit and connected to said sub-power supply line at the source of said p-channel MOS transistor.

15. A semiconductor integrated circuit according to claim 12, wherein an operation stop state is designated corresponding to a chip non-selected state.

16. A semiconductor integrated circuit according to claim 12, wherein connection points between the first sub-power supply lines and the second sub-power supply lines are arranged over said memory mats.

17. A semiconductor integrated circuit according to claim 12 or 16, wherein said memory cells are dynamic memory cells.