High speed serial link for fully duplexed data communication
First Claim
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1. A circuit for converting parallel data to a serial data comprising:
- a first register, coupled to a first clock input, to store n parallel bits of data, wherein the first register has a plurality of first outputs and a plurality of second outputs;
a second register, coupled to a second clock input and to the plurality of second outputs of the first register, wherein the second register has a plurality of third outputs; and
a plurality of n logic gates coupled to the plurality of first outputs of the first register and the plurality of third outputs of the second register.
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Abstract
A system for converting between parallel data and serial data is described. In the system 10, individual bits of the parallel data 12 are latched into individual registers 117. Each register 117 is coupled to a corresponding AND gate 110 which is also connected to receive phased clock signals. The output terminals of the AND gates 110 are connected to an OR gate 115. Using the system, with appropriately phased clocks, the parallel data is converted into serial data.
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Citations
30 Claims
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1. A circuit for converting parallel data to a serial data comprising:
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a first register, coupled to a first clock input, to store n parallel bits of data, wherein the first register has a plurality of first outputs and a plurality of second outputs; a second register, coupled to a second clock input and to the plurality of second outputs of the first register, wherein the second register has a plurality of third outputs; and a plurality of n logic gates coupled to the plurality of first outputs of the first register and the plurality of third outputs of the second register. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of converting parallel data to serial data comprising:
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providing a plurality of n different clock signals; storing n bits of parallel data in a first register; and providing the nth bit of parallel data to a serial output line during a period after a rising edge of the (n+1)th clock signal and before a rising edge of the (n+2)th clock signal. - View Dependent Claims (8, 9)
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10. A method of converting parallel data to serial data, comprising:
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providing a plurality of n different clock signals; storing n bits of parallel data in a first register; storing in a second register a subset of the n bits of parallel data stored in the first register; and providing the nth bit of parallel data to a serial output line during a period after a rising edge of the (n+1)th clock signal and before a rising edge of the (n+2)th clock signal. - View Dependent Claims (11, 12)
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13. A parallel-to-serial converter circuit comprising:
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a plurality of input lines to receive n parallel bits; at least n signal lines to receive at least n clock signals; a pull-up transistor coupled between a first supply line and a serial output data line; and a plurality of pull-down circuits, wherein each of the n parallel bits is transmitted to the corresponding nth one of the plurality of pull-down circuits, and the (n+1)th and the (n+2)th clock signals are also transmitted to the nth pull-down circuit. - View Dependent Claims (14, 15, 16)
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17. A circuit for converting parallel data to a serial data comprising:
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a first register including n input lines and at least (n+1) output lines, wherein the first register receives n parallel bits of data on the n input lines and outputs at least (n+1) bits on the at least (n+1) output lines; and at least (n+1) logic gates coupled to the at least (n+1) output lines of the first register, wherein each of the at least (n+1) logic gates are coupled to corresponding one of the at least (n+1) output lines of the first register, so that the at least (n+1) logic gates receives the n parallel bits and at least one encoding bit. - View Dependent Claims (18)
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19. A method of converting parallel data to serial data comprising:
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providing at least n different clock signals; storing n bits of parallel data in a first register; providing a rising edge of the (n+1)th clock signal; and transmitting the nth bit of parallel data to a serial output line in response to the (n+1)th clock signal. - View Dependent Claims (20, 21, 22, 23)
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24. A circuit for converting parallel data to serial data string comprising:
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a first register having a plurality of first input and first output terminals to receive and transmit the parallel data; a second register having a plurality of second input terminals coupled to the first output terminal of the first register to receive a subset of the parallel data and having a plurality of second output terminals to transmit the subject of the parallel data; and a plurality of logic gates coupled to the first output and second output terminals to receive the parallel data from the first and second registers. - View Dependent Claims (25, 26, 27, 28, 29, 30)
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Specification