High speed serial link for fully duplexed data communication

• US 6,107,946 A
• Filed: 02/03/1998
• Issued: 08/22/2000
• Est. Priority Date: 06/06/1994
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Jeong, Deog-Kyoon
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US09/017,758
• Time in Patent Office: 931 Days
• Field of Search: 341/101, 341/100, 327/407
• US Class Current: 341/101
• CPC Class Codes: H03K 19/018592 with a bidirectional operation
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 5/1423 for simultaneous baseband signals
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop

Abstract

A system for converting between parallel data and serial data is described. In the system 10, individual bits of the parallel data 12 are latched into individual registers 117. Each register 117 is coupled to a corresponding AND gate 110 which is also connected to receive phased clock signals. The output terminals of the AND gates 110 are connected to an OR gate 115. Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

Claims

1. A circuit for converting parallel data to a serial data comprising:

a first register, coupled to a first clock input, to store n parallel bits of data, wherein the first register has a plurality of first outputs and a plurality of second outputs;

a second register, coupled to a second clock input and to the plurality of second outputs of the first register, wherein the second register has a plurality of third outputs; and

a plurality of n logic gates coupled to the plurality of first outputs of the first register and the plurality of third outputs of the second register.

2. The circuit of claim 1 further comprising:

a plurality of n clock signals, each being out of phase with every other, wherein the nth clock signal is coupled to the nth logic gate.

3. The circuit of claim 2 wherein the (n+1)th clock signal is coupled to the nth logic gate.

4. The circuit of claim 1 further comprising:

a logic gate coupled to fourth outputs of the plurality of n logic gates to transmit one of the fourth outputs to a fifth output of the logic gate.

5. The circuit of claim 1 wherein the stored n parallel bits of data comprises a plurality of received parallel bits and a logical 1 and a logical 0.

6. The circuit of claim 1 wherein the first register and the second register comprises D-type flip-flops.

7. A method of converting parallel data to serial data comprising:

providing a plurality of n different clock signals;

storing n bits of parallel data in a first register; and

providing the nth bit of parallel data to a serial output line during a period after a rising edge of the (n+1)th clock signal and before a rising edge of the (n+2)th clock signal.

8. The method of claim 7 wherein each of the n different clock signals is out of phase with every other clock signal of the n different clock signals.

9. The method of claim 7 wherein a logical 1 is transferred to the serial output line on or after receiving the nth clock signal but before receiving the (n+1)th clock signal.

10. A method of converting parallel data to serial data, comprising:

providing a plurality of n different clock signals;

storing n bits of parallel data in a first register;

storing in a second register a subset of the n bits of parallel data stored in the first register; and

providing the nth bit of parallel data to a serial output line during a period after a rising edge of the (n+1)th clock signal and before a rising edge of the (n+2)th clock signal.

11. The method of claim 10 wherein each of the n different clock signals is out of phase with every other clock signal of the n different clock signals.

12. The method of claim 10 wherein a logical 1 is transferred to the serial output line on or after receiving the nth clock signal but before receiving the (n+1)th clock signal.

13. A parallel-to-serial converter circuit comprising:

a plurality of input lines to receive n parallel bits;

at least n signal lines to receive at least n clock signals;

a pull-up transistor coupled between a first supply line and a serial output data line; and

a plurality of pull-down circuits, wherein each of the n parallel bits is transmitted to the corresponding nth one of the plurality of pull-down circuits, and the (n+1)th and the (n+2)th clock signals are also transmitted to the nth pull-down circuit.

14. The circuit of claim 13 wherein each of the pull-down circuits comprises three transistors coupled in series between the serial output data line and a second supply line.

15. The circuit of claim 13 wherein the nth pull-down circuit receives an inverted version of the (n+2)th clock signal.

16. The circuit of claim 13 wherein the first supply line is VDD.

17. A circuit for converting parallel data to a serial data comprising:

a first register including n input lines and at least (n+1) output lines, wherein the first register receives n parallel bits of data on the n input lines and outputs at least (n+1) bits on the at least (n+1) output lines; and

at least (n+1) logic gates coupled to the at least (n+1) output lines of the first register, wherein each of the at least (n+1) logic gates are coupled to corresponding one of the at least (n+1) output lines of the first register, so that the at least (n+1) logic gates receives the n parallel bits and at least one encoding bit.

18. The circuit of claim 17 further comprising a second register coupled to a subset of the (n+1) output lines of the first register, wherein the second register has a plurality of output lines coupled to a subset of the at least (n+1) logic gates.

19. A method of converting parallel data to serial data comprising:

providing at least n different clock signals;

storing n bits of parallel data in a first register;

providing a rising edge of the (n+1)th clock signal; and

transmitting the nth bit of parallel data to a serial output line in response to the (n+1)th clock signal.

20. The method of claim 19 wherein each of the n different clock signals is out of phase with every other clock signal of the n different clock signals.

21. The method of claim 19 wherein a logical 1 is transferred to the serial output line on or after receiving the nth clock signal but before receiving the (n+1)th clock signal.

22. The method of claim 21 wherein the logical 1 is transferred to the serial output line during a period after a rising edge of the nth clock signal and before a rising edge of the (n+1) th clock signal.

23. The method of claim 19 further comprising storing in a second register a subset of the n bits of parallel data stored in the first register.

24. A circuit for converting parallel data to serial data string comprising:

a first register having a plurality of first input and first output terminals to receive and transmit the parallel data;

a second register having a plurality of second input terminals coupled to the first output terminal of the first register to receive a subset of the parallel data and having a plurality of second output terminals to transmit the subject of the parallel data; and

a plurality of logic gates coupled to the first output and second output terminals to receive the parallel data from the first and second registers.

25. The circuit of claim 24, wherein the first register is coupled to a first clock input, and the second register is coupled to a second clock input.

26. The circuit of claim 25 further comprising:

a plurality of n clock signals, each being out of phase with every other, wherein the nth clock signal is coupled to the nth logic gate.

27. The circuit of claim 26 wherein the (n+1)th clock signal is coupled to the nth logic gate.

28. The circuit of claim 24 further comprising:

a logic gate coupled to fourth outputs of the plurality of n logic gates to transmit one of the fourth outputs to a fifth output of the logic gate.

29. The circuit of claim 24 wherein the stored n parallel bits of data comprises a plurality of received parallel bits and a logical 1 and a logical 0.

30. The circuit of claim 24 wherein the first register and the second register comprises D-type flip-flops.