System and method for simultaneously displaying a plurality of video data objects having a different bit per pixel formats

• US 6,108,014 A
• Filed: 12/19/1996
• Issued: 08/22/2000
• Est. Priority Date: 11/16/1994
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Original Assignee: Interactive Silicon, Inc.
• Inventors: Dye, Thomas A.
• Primary Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US08/770,017
• Time in Patent Office: 1,342 Days
• Field of Search: 345/113-115, 345/132, 345/150, 345/153-155, 345/326, 345/339-346, 345/501, 345/526
• US Class Current: 345/544
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 2212/251 Local memory within processor subsystem
• CPC Class Codes: G06F 2212/253 Centralized memory
• CPC Class Codes: G06F 2212/401 Compressed data
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/28 for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A computer system and graphics controller which stores video data in memory corresponding to a plurality of video objects and presents the video objects on a video monitor, wherein a plurality of the video objects have differing numbers of bits per pixel formats. System memory stores video data in a plurality of memory areas for each of the plurality of video objects, wherein the plurality of video objects may have differing numbers of bits per pixel. The graphics controller obtains portions of the video data from the plurality of memory areas and in response provides video signals to the video monitor. The computer system and graphics controller performs pointer-based and/or display list-based video refresh operations that enable video object data to be assembled on a per window or per object basis, thereby greatly increasing the performance of the graphical display. The graphics controller maintains pointers to various areas or buffers in system memory comprising video or graphics display information. The graphics controller also manipulates respective object information workspace memory areas corresponding to each object or window, wherein the workspace areas specify data types, color depths or bits per pixel, 3D depth values, alpha blending information, screen position, etc. for the respective window or object on the screen. The graphics controller utilizes this information, as well as information received from the software driver regarding screen changes, to assemble a display refresh list in system memory. This information is used during the screen refresh to display the various windows or objects on the screen very quickly and efficiently. Thus only the number of bits per pixel required for each video object is required to be stored in memory.

Claims

1. A computer system which stores and presents video data having different bit per pixel formats, comprising:

a CPU;

a video monitor including one or more video inputs for receiving video signals and including a display screen for displaying video output comprising a plurality of video objects, wherein the display screen of the video monitor displays video output in response to video signals received at said one or more video inputs;

memory coupled to the CPU which stores video data in a plurality of memory areas, wherein said plurality of memory areas store video data for said plurality of video objects, wherein each of said memory areas stores video data corresponding to one of said plurality of video objects, wherein a plurality of said plurality of memory areas are non-contiguous, wherein a plurality of said plurality of memory areas store video data having differing numbers of bits per pixel; and

a graphics controller coupled to said CPU, said memory, and said video monitor, wherein said graphics controller obtains portions of said video data from said plurality of memory areas in said memory and in response provides video signals to said video monitor, wherein said graphics controller obtains portions of said video data having differing numbers of bits per pixel.

2. The computer system of claim 1,

wherein said memory includes a first memory area storing first video data corresponding to a first video object, wherein said first video data has a first number of bits per pixel;

wherein said memory includes a second memory area storing second video data corresponding to a second video object, wherein said second video data has a second number of bits per pixel;

wherein said graphics controller obtains portions of said first video data from said first memory area having said first number of bits per pixel, and said graphics controller obtains portions of said second video data from said second memory area having said second number of bits per pixel, and in response provides video signals to said video monitor.

3. The computer system of claim 2,

wherein said video monitor displays a first video object comprising a first number of bits per pixel and wherein said video monitor displays a second video object comprising a second number of bits per pixel.

4. The computer system of claim 1,

wherein said graphics controller maintains a plurality of object information areas in said memory which each correspond to a respective one of said objects appearing on said video monitor, wherein said plurality of object information areas comprise information regarding said objects displayed on said video monitor, wherein each of said one or more object information areas comprises information indicating a number of bits per pixel;

wherein said graphics controller uses said information in said object information areas to obtain said at least portions of said video data from said one or more of said plurality of memory areas in said memory and provide said video signals to said video monitor.

5. The computer system of claim 1,

wherein said graphics controller includes a data path for transmitting video data from said memory to said video monitor, wherein said data path has a width, wherein said graphics controller dynamically adjusts said data path width depending on the number of bits per pixel of said video data obtained from said one or more of said plurality of memory areas in said memory.

6. The computer system of claim 1, wherein said graphics controller converts all of said video data to video display data having a single bit per pixel format, the computer system further comprising:

a display storage buffer coupled between said graphics controller and said video monitor for storing said video display data having said single bit per pixel format.

7. The computer system of claim 1,

wherein said graphics controller maintains a display list comprising a plurality of pointers which point to at least portions of said video data in one or more of said plurality of memory areas in said memory;

wherein said graphics controller uses said plurality of pointers comprised in said display list to obtain said at least portions of said video data from said one or more of said plurality of memory areas in said memory;

wherein said graphics controller provides said video signals to said video monitor in response to said graphics controller obtaining said at least portions of said video data from said one or more of said plurality of memory areas in said memory.

8. The computer system of claim 7, wherein said video monitor displays data on said display screen using a plurality of scan lines;

wherein said plurality of pointers comprising said display list are ordered according to how said video data referenced by said pointers appears on respective scan lines as said scan lines are drawn on the display screen;

wherein said graphics controller uses said plurality of pointers in said order to obtain video data from said plurality of memory areas in said memory for respective scan lines as said scan lines are drawn on the display screen of said video monitor.

9. The computer system of claim 8, wherein at least one of said plurality of scan lines comprised on said video monitor displays first video data corresponding to a first video object stored in a first memory area and displays second video data corresponding to a second video object stored in a second memory area, wherein said first video object has a first number of bits per pixel and said second video object has a second number of bits per pixel.

10. The computer system of claim 9,

wherein said graphics controller includes a data path for transmitting video data from said memory to said video monitor, wherein said data path has a width, wherein said graphics controller dynamically adjusts said data path width depending on the number of bits per pixel of said video data obtained from said one or more of said plurality of memory areas in said memory;

wherein said graphics controller dynamically adjusts said data path width to a first width when transferring said first video data having said first number of bits per pixel, and said graphics controller dynamically adjusts said data path width to a second width when transferring said second video data having said second number of bits per pixel.

11. The computer system of claim 8, wherein at least one of said plurality of scan lines comprised on said video monitor displays video data corresponding to a first plurality of objects from a first plurality of memory areas;

wherein said plurality of pointers comprising said display list include a first plurality of pointers corresponding to said at least one of said plurality of scan lines, wherein said first plurality of pointers reference video data portions from said first plurality of memory areas corresponding to said first plurality of objects;

wherein said graphics controller uses said first plurality of pointers to obtain said video data portions from said first plurality of memory areas for said at least one of said plurality of scan lines when said scan line is drawn on the display screen.

12. The computer system of claim 8, wherein said display screen of said video monitor displays a first video object comprising at least portions of a first plurality of scan lines comprised on said video monitor;

wherein said memory includes a first memory area storing video data corresponding to said first video object;

wherein said plurality of pointers comprising said display list include a first plurality of pointers which reference video data portions from said first memory area corresponding to said first object;

wherein said first plurality of pointers reference video data portions of said first object corresponding to said at least portions of said first plurality of scan lines;

wherein said graphics controller uses said first plurality of pointers to obtain said video data portions from said first memory area for said plurality of scan lines when said scan lines are drawn on the display screen.

13. The computer system of claim 7, wherein said graphics controller includes an input for receiving video display information regarding desired changes to said video output of said video monitor;

wherein, in response to said video display information, said graphics controller assembles a new display list to effect desired changes on said video output of said video monitor, wherein said new display list comprises a second plurality of pointers;

wherein said graphics controller uses said second plurality of pointers in said new display list to read portions of said video data from said plurality of memory areas in said memory and provide video signals to said video monitor according to said desired changes to said video monitor.

14. The computer system of claim 7, wherein said graphics controller includes an input for receiving video display information regarding desired changes to said video output of said video monitor;

wherein, in response to said video display information, said graphics controller manipulates one or more of said plurality of pointers in said display list to effect desired changes on said video output of said video display monitor;

wherein said graphics controller uses said manipulated plurality of pointers in said display list to read portions of said video data from said plurality of memory areas in said memory and provide said video signals to said video display monitor according to said desired changes to said video display monitor.

15. The computer system of claim 7, wherein said video display monitor displays a plurality of objects;

wherein said graphics controller maintains a plurality of object information areas in said memory which each correspond to a respective one of said objects appearing on said video display monitor, wherein said plurality of object information areas comprise information regarding said objects displayed on said video display monitor;

wherein said graphics engine uses said information in said object information areas to assemble said display list.

16. The computer system of claim 15, wherein said graphics controller includes an input for receiving video display information regarding desired changes to said video output of said video monitor;

wherein, in response to said video display information, said graphics controller manipulates information in one or more of said object information areas;

wherein said graphics controller uses said manipulated information in said one or more object information areas to assemble said display list.

17. The computer system of claim 16, wherein said one or more object information areas include workspace areas which correspond to respective objects on said video monitor;

wherein each of said one or more workspace areas comprises location information including an x,y location of a respective object appearing on said video monitor;

wherein each of said one or more workspace areas further comprises information indicating a number of bits per pixel.

18. The computer system of claim 16,

wherein each of said one or more workspace areas further includes a static address pointer which points to an area in said system memory storing video data for a respective object, and a dynamic linear address pointer which points video data portions in said areas of system memory which correspond to horizontal span lines on said video display monitor, wherein said dynamic linear address pointer is used to increment through horizontal span lines of said object pointed to by said static pointer.

19. The computer system of claim 15, wherein said one or more object information areas include an ID list comprising pointer entries which each correspond to a video object on said video monitor;

wherein each of said ID list pointer entries point to respective ones of said one or more object information areas in said memory, wherein said one or more pointers in said windows ID list correspond to said objects appearing on said video monitor.

20. The computer system of claim 7, wherein said graphics controller maintains a foreground display list of address pointers and a background display list of address pointers, wherein each of said foreground and background display lists point to respective areas in said system memory storing video data;

wherein said graphics controller alternates use of said foreground display list and background display list to provide said video signals to said video display monitor during screen refresh.

21. The computer system of claim 7, wherein said graphics controller includes an execution engine which assembles said display list comprising said plurality of pointers;

wherein said graphics controller further includes a display list refresh engine which uses said plurality of pointers in said display list to read portions of said video data and provide said video signals to said video monitor.

22. The computer system of claim 21, wherein said graphics controller includes an input for receiving video display information regarding desired changes to said video output of said video monitor;

wherein said execution engine assembles a new display list comprising a second plurality of pointers in response to receiving said video display information;

wherein said display list refresh engine uses said second plurality of pointers in said new display list to read portions of said video data and provide said video signals to said video display monitor according to said desired changes to said video output of said video display monitor.

23. The computer system of claim 21, wherein said plurality of memory areas are non-contiguous.

24. The computer system of claim 1, wherein said graphics controller includes one or more video ports for providing video signals directly to said video display monitor.

25. The computer system of claim 1, wherein said memory is system memory which stores code and data used by said CPU for executing one or more applications.

26. The computer system of claim 1,

wherein said graphics controller maintains a plurality of object information areas in said memory which each correspond to a respective one of said objects stored in said memory areas, wherein each of said object information areas includes bit per pixel information indicating a number of bits per pixel for its corresponding object;

wherein said graphics controller includes a data path for transmitting video data from said memory to said video monitor, wherein said data path has a width, wherein said graphics controller uses said bit per pixel information in said object information areas to dynamically adjust said data path width for the number of bits per pixel of the respective objects being transferred through the data path for display.

27. The computer system of claim 1,

wherein said graphics controller maintains at least one data structure in said memory which comprises bit per pixel information indicating a number of bits per pixel for each of said objects;

wherein said graphics controller includes a data path for transmitting video data from said memory to said video monitor, wherein said data path has a width, wherein said graphics controller uses said bit per pixel information in said at least one data structure to dynamically adjust said data path width depending on the number of bits per pixel for the object being transferred through the data path for display.

28. The computer system of claim 27,

wherein said graphics controller maintains a plurality of data structures in said memory which each correspond to a respective one of said objects stored in said memory areas, wherein each of said data structures comprises bit per pixel information indicating a number of bits per pixel for its corresponding object;

wherein said graphics controller uses said bit per pixel information in a respective data structure to dynamically adjust said data path width depending on the number of bits per pixel for the corresponding object being transferred through the data path for display.

29. The computer system of claim 1,

wherein the graphics controller dynamically operates to selectively obtain portions of said video data from said plurality of memory areas in said memory in response to software executing on the CPU.

30. The system of claim 29, wherein the CPU dynamically provides video display information to the graphics controller indicating desired changes to the video output of the display device;

wherein the graphics controller dynamically operates to selectively obtain portions of said video data from said plurality of memory areas in response to said received video display information.

31. The system of claim 1, wherein the graphics controller obtains said video data from one or more of said plurality of memory areas in said memory on pixel span line segment boundaries.

32. The system of claim 1, wherein said plurality of memory areas are not organized in a frame buffer format.

33. The system of claim 1, wherein pixels comprised in the plurality of memory areas are not organized in a row/column manner which directly corresponds to rows/columns of the display device.

34. A graphics system for storing video data and for providing video signals to a display device, the graphics system comprising:

memory including a plurality of memory areas which store video data for a plurality of video objects, wherein each of said memory areas stores video data corresponding to one of the plurality of video objects, wherein a plurality of said plurality of memory areas are non-contiguous, wherein a plurality of said plurality of memory areas store video data having differing numbers of bits per pixel; and

a graphics controller coupled to said memory and including an output for coupling to the display device, wherein said graphics controller obtains at least portions of said video data from said plurality of memory areas in said memory and in response provides video signals to the display device, wherein said graphics controller obtains portions of said video data having differing numbers of bits per pixel.

35. The graphics system of claim 34,

wherein said memory includes a first memory area storing first video data corresponding to a first video object, wherein said first video data has a first number of bits per pixel;

wherein said memory includes a second memory area storing second video data corresponding to a second video object, wherein said second video data has a second number of bits per pixel;

wherein said graphics controller obtains portions of said first video data from said first memory area having said first number of bits per pixel and wherein said graphics controller obtains portions of said second video data from said second memory area having said second number of bits per pixel and in response provides video signals to the display device.

36. The graphics system of claim 34,

wherein said graphics controller maintains a plurality of object information areas in said memory which each correspond to a respective one of said objects, wherein said plurality of object information areas comprise information regarding said objects, wherein each of said one or more object information areas comprises information indicating a number of bits per pixel;

wherein said graphics controller uses said information in said object information areas to obtain said at least portions of said video data from said plurality of said plurality of memory areas in said memory and provide said video signals to the display device.

37. The graphics system of claim 34,

wherein said graphics controller includes a data path for transmitting video data from said memory to said display device, wherein said data path has a width, wherein said graphics controller dynamically adjusts said data path width depending on the number of bits per pixel of said video data obtained from said plurality of said plurality of memory areas in said memory.

38. The graphics system of claim 34,

wherein said graphics controller maintains a plurality of object information areas in said memory which each correspond to a respective one of said objects stored in said memory areas, wherein each of said object information areas includes bit per pixel information indicating a number of bits per pixel for its corresponding object;

wherein said graphics controller includes a data path for transmitting video data from said memory to said display device, wherein said data path has a width, wherein said graphics controller uses said bit per pixel information in said object information areas to dynamically adjust said data path width for the number of bits per pixel of the respective objects being transferred through the data path for display.

39. The graphics system of claim 34,

wherein said graphics controller maintains at least one data structure in said memory which comprises bit per pixel information indicating a number of bits per pixel for each of said objects;

wherein said graphics controller includes a data path for transmitting video data from said memory to said display device, wherein said data path has a width, wherein said graphics controller uses said bit per pixel information in said at least one data structure to dynamically adjust said data path width depending on the number of bits per pixel for the object being transferred through the data path for display.

40. The graphics system of claim 39,

wherein said graphics controller maintains a plurality of data structures in said memory which each correspond to a respective one of said objects stored in said memory areas, wherein each of said data structures comprises bit per pixel information indicating a number of bits per pixel for its corresponding object;

wherein said graphics controller uses said bit per pixel information in a respective data structure to dynamically adjust said data path width depending on the number of bits per pixel for the corresponding object being transferred through the data path for display.

41. The graphics system of claim 34, wherein said graphics controller converts all of said video data to video display data having a single bit per pixel format, the graphics system further comprising:

a display storage buffer coupled between said graphics controller and said display device for storing said video display data having said single bit per pixel format.

42. The graphics system of claim 34,

wherein said graphics controller maintains a display list comprising a plurality of pointers which point to at least portions of said video data in one or more of said plurality of memory areas in said memory;

wherein said graphics controller uses said plurality of pointers comprised in said display list to obtain said at least portions of said video data from said plurality of said plurality of memory areas in said memory;

wherein said graphics controller provides said video signals to the display device in response to said graphics controller obtaining said at least portions of said video data from said plurality of said plurality of memory areas in said memory.

43. The graphics system of claim 42, wherein said display device displays data on a display screen using a plurality of scan lines;

wherein said plurality of pointers comprising said display list are ordered according to how said video data referenced by said pointers appears on respective scan lines as said scan lines are drawn on the display screen;

wherein said graphics controller uses said plurality of pointers in said order to obtain video data from said plurality of said plurality of memory areas in said memory for respective scan lines as said scan lines are drawn on the display screen of said display device.

44. The graphics system of claim 34, wherein said plurality of memory areas are non-contiguous.

45. The system of claim 34,

wherein the graphics controller dynamically operates to selectively obtain portions of said video data from said plurality of memory areas in response to received video display information;

wherein said video display information is generated in response to program execution.

46. The graphics system of claim 34, wherein the graphics controller obtains said video data from one or more of said plurality of memory areas in said memory on pixel span line segment boundaries.

47. The graphics system of claim 34, wherein pixels comprised in the plurality of memory areas are not organized in a row/column manner which directly corresponds to rows/columns of the display device.

48. A memory for storing video data that is output to a display device, the memory comprising:

a plurality of memory areas which store video data for a plurality of video objects, wherein each of said memory areas stores video data corresponding to one of the plurality of video objects, wherein a plurality of said plurality of memory areas are non-contiguous, wherein a plurality of said plurality of memory areas store video data having differing numbers of bits per pixel; and

a plurality of data structures corresponding to each of said video objects in said memory areas, wherein each of said data structures includes bit per pixel information indicating a number of bits per pixel for its corresponding object;

a display list comprising a plurality of pointers, wherein said display list comprising said plurality of pointers is for accessing said video data from a plurality of said plurality of video objects within said plurality of memory areas for display on the display device.

49. The memory of claim 48, wherein said plurality of pointers are ordered in said display list to access said video data for said plurality of video objects within said memory areas as said video objects are displayed in horizontal scan lines on the display device.

50. The memory of claim 48, wherein said plurality of memory areas are non-contiguous.

51. A method for displaying video data on a display device, the method comprising:

storing video data in a plurality of different memory areas in a memory for a plurality of video objects, wherein each of said memory areas stores video data corresponding to one of the plurality of video objects, wherein a plurality of said plurality of memory areas are non-contiguous, wherein a plurality of said plurality of memory areas store video data having differing numbers of bits per pixel; and

obtaining at least portions of said video data from said plurality of memory areas in said memory, wherein said obtaining includes obtaining portions of said video data having differing numbers of bits per pixel; and

providing video signals to the display device in response to said obtaining.

52. The method of claim 51, further comprising:

displaying an image in response to said video signals, wherein said image includes video objects which are stored in said memory areas with different bit per pixel formats.

53. The method of claim 51,

wherein said storing video data includes storing first video data corresponding to a first video object in a first memory area, wherein said first video data has a first number of bits per pixel;

wherein said storing video data includes storing second video data corresponding to a second video object in a second memory area, wherein said second video data has a second number of bits per pixel;

wherein said obtaining includes obtaining portions of said first video data from said first memory area having said first number of bits per pixel and obtaining portions of said second video data from said second memory area having said second number of bits per pixel.

54. The method of claim 53, further comprising:

displaying said first video object comprising said first number of bits per pixel; and

displaying said second video object comprising said second number of bits per pixel.

55. The method of claim 51, further comprising:

maintaining a plurality of object information areas in said memory which each correspond to a respective one of said objects stored in said memory areas, wherein said plurality of object information areas comprise information regarding said objects, wherein each of said object information areas comprises information indicating a number of bits per pixel;

wherein said obtaining includes using said information in said object information areas to obtain said at least portions of said video data from said plurality of said plurality of memory areas in said memory.

56. The method of claim 51,

wherein said providing video signals to the display device includes transmitting video data from said memory to said display device on a data path, wherein said data path has a width, wherein said providing video signals to the display device includes dynamically adjusting said data path width depending on the number of bits per pixel of said video data obtained from said plurality of said plurality of memory areas in said memory.

57. The method of claim 51, further comprising:

maintaining a plurality of object information areas in said memory which each correspond to a respective one of said objects stored in said memory areas, wherein each of said object information areas includes bit per pixel information indicating a number of bits per pixel for its corresponding object;

wherein said providing video signals to the display device includes transmitting video data from said memory to said display device on a data path, wherein said data path has a width, wherein said providing video signals to the display device includes dynamically adjusting said data path width in response to said bit per pixel information in said object information areas.

58. The method of claim 51, further comprising:

maintaining at least one data structure in said memory which comprises bit per pixel information indicating a number of bits per pixel for each of said objects;

wherein said providing video signals to the display device includes transmitting video data from said memory to said display device on a data path, wherein said data path has a width, wherein said providing video signals to the display device includes dynamically adjusting said data path width for the object being transferred through the data path in response to respective bit per pixel information in said at least one data structure.

59. The method of claim 58,

wherein said maintaining comprises maintaining a plurality of data structures in said memory which each correspond to a respective one of said objects stored in said memory areas, wherein each of said data structures comprises bit per pixel information indicating a number of bits per pixel for its corresponding object;

wherein said providing video signals includes using said bit per pixel information in a respective data structure to dynamically adjust said data path width depending on the number of bits per pixel for the corresponding object being transferred through the data path for display.

60. The method of claim 51, wherein said providing video signals to the display device includes converting all of said video data to video display data having a single bit per pixel format.

61. The method of claim 51, further comprising:

maintaining a display list comprising a plurality of pointers which point to at least portions of said video data in one or more of said plurality of memory areas in said memory;

wherein said obtaining portions of said video data includes using said plurality of pointers comprised in said display list to obtain said at least portions of said video data from said one or more of said plurality of memory areas in said memory.

62. The method of claim 61, wherein said display device displays data on a display screen using a plurality of scan lines;

wherein said plurality of pointers comprising said display list are ordered according to how said video data referenced by said pointers appears on respective scan lines as said scan lines are drawn on the display screen;

wherein said obtaining portions of said video data includes using said plurality of pointers in said order to obtain video data from said plurality of memory areas in said memory for respective scan lines as said scan lines are drawn on the display screen of said display device.

63. The method of claim 51,

wherein said obtaining and said providing are dynamically performed a plurality of times in response to software executing on a CPU.

64. The method of claim 63, further comprising:

executing a software application on a CPU;

wherein said obtaining and said providing are dynamically performed in response to the software application executing on the CPU;

wherein the software application executing on the CPU dynamically controls said obtaining to selectively obtain said portions of said video data from said plurality of said plurality of memory areas in said memory.

65. The method of claim 64, further comprising:

dynamically generating video display information indicating desired changes to the video output of the display device in response to the software application executing;

wherein said selectively obtaining is dynamically performed in response to said video display information.

66. The method of claim 51, wherein said plurality of memory areas are not organized in a frame buffer format.

67. The method of claim 51, wherein said obtaining obtains said video data from one or more of said plurality of memory areas in said memory on pixel span line segment boundaries.

68. The method of claim 51,

wherein said obtaining obtains only a portion of the video data from a plurality of said plurality of memory areas in said memory;

wherein said providing provides video signals to said display device in response to said portions of the video data.

69. A system which stores and presents video data having different bit per pixel formats, comprising:

a CPU;

a display device including one or more video inputs for receiving video signals and including a display screen for displaying video output comprising a plurality of video objects, wherein the display screen of the display device displays video output in response to video signals received at said one or more video inputs;

memory coupled to the CPU which stores video data in a plurality of memory areas, wherein said plurality of memory areas store video data for said plurality of video objects, wherein each of said memory areas stores video data corresponding to one of said plurality of video objects, wherein a plurality of said plurality of memory areas are non-contiguous, and wherein a plurality of said plurality of memory areas store video data having differing numbers of bits per pixel; and

a graphics controller coupled to said CPU, said memory, and said display device, wherein said graphics controller obtains portions of said video data from said plurality of memory areas in said memory and in response provides video signals to said display device, wherein said graphics controller obtains portions of said video data having differing numbers of bits per pixel.

70. The system of claim 69,

wherein said memory includes a first memory area storing first video data corresponding to a first video object, wherein said first video data has a first number of bits per pixel;

wherein said memory includes a second memory area storing second video data corresponding to a second video object, wherein said second video data has a second number of bits per pixel;

wherein said graphics controller obtains portions of said first video data from said first memory area having said first number of bits per pixel, and said graphics controller obtains portions of said second video data from said second memory area having said second number of bits per pixel, and in response provides video signals to said display device.

71. The system of claim 69,

wherein said graphics controller maintains a plurality of object information areas in said memory which each correspond to a respective one of said objects appearing on said display device, wherein said plurality of object information areas comprise information regarding said objects displayed on said display device, wherein each of said one or more object information areas comprises information indicating a number of bits per pixel;

wherein said graphics controller uses said information in said object information areas to obtain said at least portions of said video data from said one or more of said plurality of memory areas in said memory and provide said video signals to said display device.

72. The system of claim 69,

wherein said graphics controller includes a data path for transmitting video data from said memory to said display device, wherein said data path has a width, wherein said graphics controller dynamically adjusts said data path width depending on the number of bits per pixel of said video data obtained from said one or more of said plurality of memory areas in said memory.

73. The system of claim 69, wherein said graphics controller converts all of said video data to video display data having a single bit per pixel format, the computer system further comprising:

a display storage buffer coupled between said graphics controller and said display device for storing said video display data having said single bit per pixel format.

74. The system of claim 69,

wherein said graphics controller maintains a plurality of object information areas in said memory which each correspond to a respective one of said objects stored in said memory areas, wherein each of said object information areas includes bit per pixel information indicating a number of bits per pixel for its corresponding object;

wherein said graphics controller includes a data path for transmitting video data from said memory to said display device, wherein said data path has a width, wherein said graphics controller uses said bit per pixel information in said object information areas to dynamically adjust said data path width for the number of bits per pixel of the respective objects being transferred through the data path for display.

75. The system of claim 69,

wherein said graphics controller maintains at least one data structure in said memory which comprises bit per pixel information indicating a number of bits per pixel for each of said objects;

wherein said graphics controller includes a data path for transmitting video data from said memory to said display device, wherein said data path has a width, wherein said graphics controller uses said bit per pixel information in said at least one data structure to dynamically adjust said data path width depending on the number of bits per pixel for the object being transferred through the data path for display.

76. The system of claim 69,

wherein the graphics controller dynamically operates to selectively obtain portions of said video data from said plurality of memory areas in said memory in response to software executing on the CPU.

77. The system of claim 69, wherein the graphics controller obtains said video data from one or more of said plurality of memory areas in said memory on pixel span line segment boundaries.

78. The system of claim 69, wherein pixels comprised in the plurality of memory areas are not organized in a row/column manner which directly corresponds to rows/columns of the display device.

79. The system of claim 69, wherein said graphics controller includes one or more video ports for providing video signals directly to said display device.

80. The system of claim 69, wherein said memory is system memory which stores code and data used by said CPU for executing one or more applications.