Flash memory with split gate structure and method of fabricating the same
First Claim
1. A flash memory with a split gate structure formed on a substrate, the flash memory comprising:
- a channel region in the substrate;
a tunneling oxide, covering a first part of the channel region;
a floating gate, having a gradually diffusion profile from a bottom surface of the floating gate beside the substrate to a top surface of the floating gate opposite to the bottom surface;
a spacer, covering a first sidewall of the floating gate;
a dielectric layer, covering the top surface of the floating gate and a second sidewall of the floating gate and a second part of the channel region;
a control gate, on the dielectric layer; and
a source region, in the substrate next to the spacer on the first sidewall of the floating gate, anda drain region, in the substrate next to the control gate over the second sidewall of the floating gate.
1 Assignment
0 Petitions
Accused Products
Abstract
A flash memory with a split gate. The flash memory is formed on a semiconductor substrate, comprising a channel region, a tunnel oxide layer, a floating gate, a control gate, a dielectric layer and two source/drain regions. The channel region is located on a surface of the semiconductor substrate and partly covered by the floating gate. The floating gate is funnelform, that is, having a gradually diffusing cross sectional profile from a bottom surface to a top surface, and has a tunnel oxide layer to isolate with the semiconductor substrate, and there is an annulus tip on the rim of the top surface. The dielectric layer is located on a part of the top surface and a sidewall of the floating gate and a part of the channel region uncovered by the floating gate. The control gate is formed on the dielectric layer, and the source/drain regions are formed in the semiconductor at both sides of the channel region. The flash memory further comprises a reverse triangular doped region is formed by a delta doping step, and therefore, the source line capacitance is reduced to be advantageous to anti-punch through effect. Further, compared to conventional method, the annulus tip with a sharper profile has a greatly improved operation speed with a reduced erasure voltage.
9 Citations
8 Claims
-
1. A flash memory with a split gate structure formed on a substrate, the flash memory comprising:
-
a channel region in the substrate; a tunneling oxide, covering a first part of the channel region; a floating gate, having a gradually diffusion profile from a bottom surface of the floating gate beside the substrate to a top surface of the floating gate opposite to the bottom surface; a spacer, covering a first sidewall of the floating gate; a dielectric layer, covering the top surface of the floating gate and a second sidewall of the floating gate and a second part of the channel region; a control gate, on the dielectric layer; and a source region, in the substrate next to the spacer on the first sidewall of the floating gate, and a drain region, in the substrate next to the control gate over the second sidewall of the floating gate. - View Dependent Claims (2, 3, 4)
-
-
5. A split gate structure suitable for use in a flash memory on a substrate, the split gate structure comprising:
-
a tunneling oxide on the substrate; a floating gate on the tunneling oxide, having a funnel profile with a larger bottom surface of the floating gate beside the substrate and a smaller top surface of the floating gate opposite to the bottom surface, the floating gate further having a first sidewall covered by a spacer and a second sidewall; a dielectric layer, formed on the top surface and the second sidewall of the floating gate and extending on a part of the substrate uncovered by the tunneling oxide next to the second sidewall; and a control gate on the dielectric layer. - View Dependent Claims (6, 7, 8)
-
Specification
-
- Resources
-
Current AssigneeTaiwan Semiconductor Manufacturing Company Limited
-
Original AssigneeTaiwan Semiconductor Manufacturing Company Limited
-
InventorsChen, Hsin-Ming, Lin, Chrong-Jung
-
Primary Examiner(s)Fears, Terrell W.
-
Application NumberUS09/371,702Time in Patent Office378 DaysField of Search365/185.33, 365/185.29, 365/51US Class Current365/185.33CPC Class CodesH10B 41/30 characterised by the memory...
