Satellite payload processing system providing on-board rate alignment
First Claim
1. A rate alignment apparatus for a satellite comprising:
- an on-board clock;
an input switch;
an output switch;
a ping-pong buffer pair comprising first and second buffers and connected to said input switch and said output switch, said first and second buffers each receiving a stream of digital baseband symbols recovered from an uplink signal depending on the operation of said input switch and said output switch, said first buffer of said buffer pair receiving bits in said stream in accordance with an uplink clock rate obtained from said uplink signal, said second buffer of said buffer pair substantially simultaneously emptying the stored contents thereof in accordance with said on-board clock, the operations of said first and second buffers being reversed upon actuation of said input switch and said output switch;
first and second correlators connected to said first and second buffers, respectively, and operable to generate a spike when a header denoting a frame in said stream of baseband symbols is detected, said buffer pair being operable to continue to write said stream of baseband symbols into one of said buffer pair until said spike occurs, said input switch and said output switch being switched to the reverse states thereof, said first and second buffer receiving said uplink signal being read to the output thereof in accordance with said on-board clock rate;
a sychronized pulse oscillator connected to said first and second correlators and operable to generate a smoothed pulse for each of said symbols read to said output; and
a counter connected to said oscillator to count said smoothed pulses, a number of bits being added to or removed from said header being read to said output in accordance with the value of said counter.
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Accused Products
Abstract
A rate alignment apparatus for a satellite includes an on-board clock, an input switch, an output switch and a ping-pong buffer pair including first and second buffers and connected to the input switch and the output switch. The first and second buffers receive a stream of digital baseband symbols recovered from an uplink signal depending on the operation of the input switch and the output switch. The first buffer of the buffer pair receives the bits in accordance with an uplink clock rate obtained from the uplink signal. The second buffer of the buffer pair substantially simultaneously empties the stored contents thereof to a third buffer in accordance with the on-board clock, the operations of the first and second buffers being reversed upon actuation of the input switch and the output switch. First and second correlators generate a spike when a header denoting when a frame in the stream of baseband symbols is detected. The buffer pair is operable to continue to write the stream of baseband symbols into one of the buffer pair until the spike occurs. The input switch and the output switch are switched to their reverse states, and the first and second buffers the uplink signal are read to the output thereof in accordance with the on-board clock rate. A sychronized pulse oscillator connected to the first and second correlators generates a smoothed pulse for each of the symbols read to the output. A counter connected to the oscillator counts the smoothed pulses. A number of bits is added to or removed from the headers of the streams in accordance with the value of the counter.
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Citations
4 Claims
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1. A rate alignment apparatus for a satellite comprising:
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an on-board clock; an input switch; an output switch; a ping-pong buffer pair comprising first and second buffers and connected to said input switch and said output switch, said first and second buffers each receiving a stream of digital baseband symbols recovered from an uplink signal depending on the operation of said input switch and said output switch, said first buffer of said buffer pair receiving bits in said stream in accordance with an uplink clock rate obtained from said uplink signal, said second buffer of said buffer pair substantially simultaneously emptying the stored contents thereof in accordance with said on-board clock, the operations of said first and second buffers being reversed upon actuation of said input switch and said output switch; first and second correlators connected to said first and second buffers, respectively, and operable to generate a spike when a header denoting a frame in said stream of baseband symbols is detected, said buffer pair being operable to continue to write said stream of baseband symbols into one of said buffer pair until said spike occurs, said input switch and said output switch being switched to the reverse states thereof, said first and second buffer receiving said uplink signal being read to the output thereof in accordance with said on-board clock rate; a sychronized pulse oscillator connected to said first and second correlators and operable to generate a smoothed pulse for each of said symbols read to said output; and a counter connected to said oscillator to count said smoothed pulses, a number of bits being added to or removed from said header being read to said output in accordance with the value of said counter. - View Dependent Claims (2, 3)
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4. A method of aligning the rate of uplink symbols to an on-board clock on a satellite, the on-board clock being operable to generate clock ticks, the method comprising the steps of:
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filling a buffer with a plurality of said symbols at a received symbol rate; correlating said symbols in said buffer into frames by comparing a header inserted amongst said symbols with a unique framing word to locate said header amongst said symbols stored in said buffer and generating correlation spikes when said header is located; determining the number of clock ticks that are generated by said on-board symbol clock between said correlation spikes, said number of clock ticks corresponding to an on-board symbol rate; and adjusting the length of said header in said buffer to compensate for a rate difference between said received symbol rate and said on-board symbol rate.
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Specification