Optoelectronic integrated circuits formed of polycrystalline semiconductor waveguide

• US 6,108,464 A
• Filed: 10/13/1998
• Issued: 08/22/2000
• Est. Priority Date: 11/26/1996
• Status: Expired due to Fees

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Black, Marcie R., Foresi, James S., Koker, Debra M., Agarwal, Anu M., Kimerling, Lionel C.
• Primary Examiner(s): Ullah, Akm E.
• Application Number:
  US09/170,937
• Time in Patent Office: 679 Days
• Field of Search: 385/14, 385/131, 385/129, 385/130, 385/132, 385/147, 257/17, 257/20, 257/21, 257/85, 257/98, 257/459, 359/248, 438/180, 438/39, 438/571, 438/969, 438/71, 438/97, 427/571, 427/573, 427/575
• US Class Current: 385/14
• CPC Class Codes: G02B 2006/12169 Annealing
• CPC Class Codes: G02B 6/10 of the optical waveguide type G02B6/02, G02B6/24 take precedence; devices or arrangements for the control of light by electric, magnetic, electro-magnetic or acoustic means G02F1/00; transferring the modulation of modulated light G02F2/00; optical logic elements G02F3/00; optical analogue/digital converters G02F7/00
• CPC Class Codes: G02B 6/12004 Combinations of two or more optical elements
• CPC Class Codes: G02B 6/122 Basic optical elements, e.g. light-guiding paths
• CPC Class Codes: G02B 6/132 by deposition of thin films

Abstract

Methods of forming polycrystalline semiconductor waveguides include the steps of forming a first cladding layer (e.g., SiO₂) on a substrate (e.g., silicon) and then forming a polycrystalline semiconductor layer (e.g., poly-Si) on the first cladding layer using a direct deposition technique or by annealing amorphous silicon (a-Si) to form a polycrystalline layer, for example. The deposited polycrystalline semiconductor layer can then be polished at a face thereof to have a root-mean-square (RMS) surface roughness of less than about 6 nm so that waveguides patterned therefrom have loss ratings of better than 35 dB/cm. The polished polycrystalline semiconductor layer is then preferably etched in a plasma to form a plurality of polycrystalline strips. A second cladding layer is then formed on the polycrystalline strips to form a plurality of polycrystalline waveguides which provide relatively low-loss paths for optical communication between one or more optoelectronic devices coupled thereto. The annealed amorphous silicon layer or deposited polycrystalline layer can also be hydrogenated by exposing the second cladding layer to a hydrogen containing plasma at a temperature and pressure of about 350° C. and 0.16 mTorr, respectively, and for a duration in a range between about 30 and 60 minutes. This further improves the loss ratings of the waveguides to about 15 dB/cm or less.

Claims

1. An optoelectronic integrated circuit, comprising:

a semiconductor substrate;

a polycrystalline semiconductor waveguide having a surface thereon with a root-mean-square surface roughness of less than about 6 nm, on said semiconductor substrate;

a cladding layer having an index of refraction less than about 0.7 times an index of refraction of said polycrystalline semiconductor waveguide, surrounding at least a portion of said polycrystalline semiconductor waveguide; and

a source of optical energy on said semiconductor substrate, coupled to an interior of said polycrystalline semiconductor waveguide to propagate a signal having a first wavelength of less than about 1.55 microns therein.

2. The optoelectronic integrated circuit of claim 1, wherein said polycrystalline semiconductor waveguide comprises a hydrogenated layer of polycrystalline silicon;

and wherein said cladding layer comprises silicon dioxide.

3. The optoelectronic integrated circuit of claim 1, wherein said polycrystalline semiconductor waveguide contains grains therein smaller than 0.4 microns.

4. The optoelectronic integrated circuit of claim 2, wherein said polycrystalline semiconductor waveguide contains grains therein smaller than 0.4 microns.