Audio data playback clock signal generating apparatus for use in digital VCR

• US 6,108,485 A
• Filed: 04/30/1998
• Issued: 08/22/2000
• Est. Priority Date: 04/30/1997
• Status: Expired due to Fees

• Current Assignee: Dongbu Daewoo Electronics Corporation (Dayou Holdings Co.,Ltd.)
• Original Assignee: Daewoo Electronics Company Limited (Dayou Holdings Co.,Ltd.)
• Inventors: Kim, Jeong-Kyu
• Primary Examiner(s): Boccio, Vincent F.
• Application Number:
  US09/069,949
• Time in Patent Office: 845 Days
• Field of Search: 386/33, 386/39, 386/96, 386/98, 386/101, 386/104-106, 386/46, 386/111-112
• US Class Current: 386/201
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels
• CPC Class Codes: H04N 5/9267 using time division multiplex of the PCM audio and PCM video signals

Abstract

An audio data playback clock signal generating apparatus of a digital VCR synchronizes an audio frame playback synchronization signal with a video frame synchronization signal when an audio data recorded in a magnetic tape is played back based on a phase error of an audio data frame size AF-SIZE and an audio data playback clock signal of the previous video frame. The audio data playback clock signal generating apparatus comprises an audio data frame size decoder, a low pass filter, a voltage-controlled oscillator, and phase error generating block and can be implemented by a large scale integration(LSI) to thereby provide a non-complex circuit and an accurate synchronization between the audio frame playback synchronization signal and the video frame synchronization signal.

Claims

1. An apparatus for generating an audio data playback clock signal by comparing a present audio data frame playback synchronization signal corresponding to a present audio data frame size AF-SIZE with a present video frame synchronization signal, calculating a phase error between the present audio frame playback synchronization signal and the present video frame synchronization signal, and adding the phase error to a next audio data frame value AFV, wherein the audio data frame values AFV are obtained by applying a predetermined manipulation on audio data frame sizes AF-SIZE'"'"'s and the phase error is generated by a phase error generation means, the apparatus comprising;

means for decoding the audio data frame size AF-SIZE representing a number of audio sample data on a frame basis and outputting the audio data frame value AFV by applying a predetermined relative equation to the audio data frame size AF-SIZE;

means for adding the audio data frame value AFV with the phase error;

a pulse width modulation means for modulating a sampling clock signal and producing a reference PWM signal PR and a variable duty ratio PWM signal PWMO, wherein the reference PWM signal PR is obtained by dividing the sampling clock which is applied by an external oscillator with a predetermined value and the variable duty ratio PWM signal PWMO is obtained by determining its duty ratio according to the reference PWM signal PR;

a filter means for filtering the variable duty ratio PWM signal PWMO and outputting a direct current Vc corresponding to the filtered variable duty ratio PWM signal PWMO;

a voltage-controlled oscillation means for generating the audio frame playback clock signal according to the direct current Vc outputted from the filter means; and

a phase error generation means for generating an audio frame playback synchronization signal based on the audio data playback clock signal and the audio data frame size AF-SIZE, comparing the audio frame playback synchronization signal with the video frame synchronization signal, and creating the phase error between the audio frame playback synchronization signal and the video frame synchronization signal based on the reference PWM signal from the pulse width modulation means.

2. The apparatus according to claim 1, wherein the audio data frame value AFV is a linearly mapped value on the audio data frame size AF-SIZE by subdividing the sampling clock signal fed from the external oscillator into 125 levels and scaling up/down the divided sampling clock signal with the difference of a maximum audio data frame size and a minimum audio data frame size.

3. The apparatus according to claim 2, wherein the audio data frame value AFV outputted from the audio data frame size decoder is produced by subtracting the minimum audio data frame size AF-SIZE_min from the audio data frame size AF-SIZE inputted to the audio data frame size decoder, multiplying 2 and adding the specific value X to the subtracted audio data frame size.

4. The apparatus according to claim 3, wherein the reference PWM signal has a duty ratio of 50% obtained by dividing the sampling clock into 125 levels.

5. The apparatus according to claim 4, wherein the phase error generating block includes:

a scaling means for generating a frequency which is near to the audio data sampling frequency by dividing the audio data playback clock signal outputted from the voltage-controlled oscillator with a predetermined value; and

a counting means for outputting an audio data playback synchronization signal by dividing the audio data sampling frequency outputted from the scaling means in accordance with the audio data frame size AF-SIZE inputted thereto.