Direct memory access apparatus for transferring a block of data having discontinous addresses using an address calculating circuit

• US 6,108,722 A
• Filed: 09/13/1996
• Issued: 08/22/2000
• Est. Priority Date: 09/13/1996
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Nielsen, Michael J. K., Moreton, Henry P., Gardner, Linda S., Fuccio, Michael L., Troeller, Mark W.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): WANG, ALBERT C
• Application Number:
  US08/713,602
• Time in Patent Office: 1,439 Days
• Field of Search: 710/24, 710/26, 710/55, 712/25, 711/206, 711/209
• US Class Current: 710/26
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A method and arrangement for a dma transfer mode having multiple transactions is provided. The invention generates a set of transaction entries for a DMA transfer each of which contains information related to the address and command instruction of a transaction. The transaction entries are stored in an address/cmd-output-FIFO. The invention negotiates for the control of the system bus. Upon gaining control of the bus, the commands and address relate to each transaction are sequentially place on the system bus. If the transaction is a read operation, data received back from the system bus is first stored in a data-in-FIFO before being sent to the desired destination. If the transaction is a write operation, the data to be transferred is first stored in a data-out-FIFO before being timely place on the system bus for transferring to the desired destination. In either case, the number of data words transferred is monitored to determine when a transaction is complete. The number of transactions carried out is also monitored to determine when a DMA transfer is complete.

Claims

1. An apparatus coupled to a central processor, a system memory, a system bus, and a local memory to perform a DMA transfer of a block of data having discontinuous memory addresses, the apparatus comprising:

an address calculating circuit coupled to the system bus which receives information regarding a block of memory locations inside the system memory, wherein the block of memory locations includes a plurality of memory location rows having discontinuous memory addresses, a memory location row having a plurality of memory locations for storing data words;

wherein the information regarding the block of memory locations comprises an address of a first memory location in a first row, a number of memory location rows, a number of data words per memory location row, and a number of memory locations to be skipped between rows; and

wherein the address calculating circuit generates a plurality of transaction entries corresponding to the number of memory location rows each having a transaction type to be carried out, a starting memory address, and data word count of each transaction.

2. The apparatus of claim 1 further comprising:

a control circuit coupled to the system bus, the control circuit determining from information provided by the transaction entries a transaction count, transaction type, starting address of a transaction, and data word count of the transaction, the control circuit carrying out the transaction by communicating with the system bus, monitoring number of data words transferred in the transaction, and monitoring number of transactions performed;

wherein the address calculating circuit communicates to the control circuit when all the transaction entries have been generated.

3. The apparatus of claim 2 further comprising:

a second FIFO buffer coupled to the system bus and the local memory, the second FIFO buffer receiving as input data from the system memory via the system bus and transferring the input data to the local memory;

wherein the control circuit compares the data transferred from the second data FIFO buffer relative to the data word count to determine the completion of a write transaction.

4. The apparatus of claim 3 further comprising:

a third FIFO buffer coupled to the local memory and the system bus, the third FIFO buffer receiving as input data from the local memory and transferring the input data to the system memory via the system bus;

wherein the control circuit compares the data transferred from the third data FIFO buffer relative to the data word count to determine the completion of a read transaction.

5. The apparatus of claim 4 further comprising:

a first FIFO buffer coupled to the system bus receiving as input the transaction entries;

wherein the address calculating circuit places a marking indicating the end of the transaction entries when providing the transaction entries to the first FIFO buffer.

6. The apparatus of claim 5, wherein the control circuit monitors the marking indicating the end of the transaction entries to determine when the DMA transfer is complete.

7. The apparatus of claim 6, wherein the control circuit communicates to the address generating circuit when the DMA transfer is complete.

8. The apparatus of claim 2, wherein the control circuit communicates with the system bus to gain control of the system bus.

9. The apparatus of claim 6 further comprising a multiplexer receiving the data transferred from the third FIFO buffer at a first input and the starting addresses from the first FIFO buffer at a second input, the multiplexer providing as an output either the data transferred from the third FIFO buffer or the starting addresses from the first FIFO buffer in response to a control signal from the control circuit.

10. The apparatus of claim 9, wherein the control circuit provides the transaction types to be carried out as command instructions and the starting addresses on the system bus such that each command instruction and a corresponding starting address are provided in a same clock cycle.

11. The apparatus of claim 10, wherein the control circuit further provides data identifiers corresponding to data on the system bus.

12. The apparatus of claim 11, wherein the control circuit provides data and the corresponding data identifiers on the system bus in a same clock cycle.

13. The apparatus of claim 12, wherein the control circuit activates a valid data signal when command instructions, starting addresses, data identifiers, and data are placed on the system bus.

14. A computer system comprising:

a system bus;

a CPU coupled to the bus;

a memory controller coupled to the bus;

a main memory coupled to the memory controller; and

a video/image processor coupled to the system bus, the video/image processor comprising;

an internal bus;

a local memory coupled to the internal bus; and

an apparatus coupled to the internal bus to perform a DMA transfer of a block of data having discontinuous memory addresses, the apparatus comprising;

a first FIFO buffer coupled to the system bus receiving as input a plurality of transaction entries, the transaction entries providing information and instructions relating to transactions to be carried out by the apparatus;

a second FIFO buffer coupled to the system bus and the local memory, the second FIFO buffer receiving as input data from the system memory via the system bus and transferring the input data to the local memory;

a third FIFO buffer coupled to the local memory and the system bus, the third FIFO buffer receiving as input data from the local memory and transferring the input data to the system memory via the system bus;

a control circuit coupled to the first FIFO buffer, the second FIFO buffer, the third FIFO buffer, and the system bus, the control circuit determining from information provided by the transaction entries transaction count, transaction type, starting address of each transaction, and data word count of each transaction, the control circuit carrying out the transactions by communicating with the system bus, monitoring number of data words transferred in a transaction, and monitoring number of transactions performed; and

an address calculating circuit coupled to the system bus which receives information regarding a block of memory locations inside the system memory, wherein the block of memory locations includes a plurality of memory location rows having discontinuous memory addresses, a memory location row having a plurality of memory locations for storing data words;

wherein the information regarding the block of memory locations comprises an address of a first memory location in a first row, a number of memory location rows, a number of data words per memory location row, and a number of memory locations to be skipped between rows; and

wherein the address calculating circuit generates a plurality of transaction entries corresponding to the number of memory location rows each having a transaction type to be carried out, a starting memory address and the data word count of each transaction.

15. The computer system of claim 14, wherein the control circuit compares the data transferred from the second data FIFO buffer relative to the data word count to determine the completion of a write transaction.

16. The computer system of claim 14, wherein the control circuit compares the data transferred from the third data FIFO buffer relative to the data word count to determine the completion of a read transaction.

17. The computer system of claim 14, wherein the address calculating circuit places a marking indicating the end of the transaction entries when providing the transaction entries to the first FIFO buffer.

18. The computer system of claim 17, wherein the control circuit monitors the marking indicating the end of the transaction entries to determine when the DMA transfer is complete.