Method and apparatus for a relaxed bus protocol using heuristics and higher level supervision

• US 6,108,734 A
• Filed: 12/01/1997
• Issued: 08/22/2000
• Est. Priority Date: 12/01/1997
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Shand, Mark Alexander
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/982,080
• Time in Patent Office: 995 Days
• Field of Search: 710/130, 710/105, 710/35, 710/22, 709/200, 709/232, 370/428, 370/912, 714/47, 714/48
• US Class Current: 710/105
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

In a relaxed bus protocol for transferring bursts of data from a slow device to another device, a predictor generates an advance signal. The advance signal is used to load next data into an output register of the slow device, the next data can then be transferred to the other device. A validator/corrector receiving a ready signal from the second device, the validator/corrector determines that the advance signal is correctly generated by the predictor. Heuristics and a higher level protocol adjust the size and frequency of the bursts of data to achieve optimal performance, and maintain correctness of transmitted data.

Claims

1. An apparatus for relaxing a bus protocol, the bus protocol for transferring bursts of data from a first device to a second device, comprising:

a predictor generating an advance signal, the advance signal to load next data into an output register of the first device, the next data to be transferred to the second device; and

a validator/corrector receiving a ready signal from the second device, the validator/corrector to determine that the advance signal is correctly generated by the predictor.

2. The apparatus of claim 1 wherein the validator/corrector adjusts the generation of the advance signal according to a pattern of ready signals received.

3. The apparatus of claim 1 wherein the validator/corrector generates an error condition when the advance signal is generated erroneously.

4. The apparatus of claim 3 wherein the error condition is an asynchronous interrupt signal.

5. The apparatus of claim 3 wherein the error condition is stored in a status register.

6. The apparatus of claim 3 wherein the error condition is an exception condition.

7. The apparatus of claim 3 wherein the error condition is processed by a higher level protocol to correct the erroneous transfer of the data.

8. The apparatus of claim 7 wherein the higher level protocol is implemented with a software device driver connected to the first device.

9. The apparatus of claim 7 wherein the higher level protocol uses a hardware circuit within the device.

10. The apparatus of claim 1 wherein the predictor includes a register for determining the length of the burst of data that can consistently be sent correctly to the second device.

11. A method for a relaxed bus protocol, the bus protocol for transferring data from a first device to a second device, comprising:

generating an advance signal in the first device, the advance signal to load next data into an output register of the first device, the next data to be transferred to the second device;

receiving a ready signal from the second device;

determining that the advance signal is correctly generated; and

transferring the data from the first device to the second device when the advance signal is correctly generated.