Layout design method and system for an improved place and route

• US 6,110,222 A
• Filed: 05/13/1998
• Issued: 08/29/2000
• Est. Priority Date: 05/13/1997
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Minami, Fumihiro, Murofushi, Masako
• Primary Examiner(s): Lintz, Paul R.
• Assistant Examiner(s): THOMPSON, ANNETTE M
• Application Number:
  US09/076,490
• Time in Patent Office: 839 Days
• Field of Search: 395/500.1, 716/9, 716/10
• US Class Current: 716/113
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A layout design method and system for a semiconductor integrated circuit improves circuit performances related to operated frequency and power consumption by improved placement and routing. The method features an intersecting wiring predicting step that predicts the number of the intersecting wirings based on predicted wiring routes and an intersecting wiring capacitance calculating step that calculates the capacitances between the intersecting wirings.

Claims

1. A design method for a semiconductor integrated circuit, comprising:

a placing step of carrying out a layout placement of the semiconductor integrated circuit;

an interwiring capacitance calculating step of calculating capacitances between adjacent wirings of the semiconductor integrated circuit which has been subjected to the layout design effected by the placing step, comprising the steps of;

a wiring route predicting step of predicting routes of wirings of the semiconductor integrated circuit;

an adjacent wiring length predicting step of predicting adjacent wiring length based on predicted routes; and

an adjacent wiring capacitance calculating step of calculating the capacitance between the adjacent wirings based on the adjacent wiring lengths being calculated;

a re-placing step of carrying out a layout re-placement of the semiconductor integrated circuit based on calculation results, comprising the steps of;

calculating a critical path by calculating delay based on the capacitances between adjacent wirings or the capacitances between intersecting wirings of the semiconductor integrated circuit,

determining whether or not the critical path has satisfied specifications,

carrying out the layout re-placement of the semiconductor integrated circuit after generating path delay constraints unless the critical path has satisfied specifications,

carrying out the calculation of the capacitances between adjacent wirings of the semiconductor integrated circuit which has been subjected to the layout re-placement,

calculating the critical path by calculating delay based on the capacitances between adjacent wirings or the capacitances between intersecting wirings of the semiconductor integrated circuit which has been subjected to the layout re-placement, and

setting a lower limit value of net wiring distance unless the critical path has satisfied specifications, and then carrying out the layout re-placement of the semiconductor integrated circuit after generating the path delay constraints.

2. A design method as claimed in claim 1, wherein the wiring route predicting step comprises the steps of,

dividing the semiconductor integrated circuit into a plurality of wiring regions,

calculating routing congestions of respective wiring regions, and

predicting the routes of respective wirings based on the routing congestions.

3. A design method as claimed in claim 1, wherein the wiring route predicting step comprises the steps of,

dividing the semiconductor integrated circuit into a plurality of wiring regions,

calculating routing congestions for respective sides of wiring regions, and

predicting the routes of respective wirings based on the routing congestions.

4. A design method as claimed in claim 1, wherein the wiring route predicting step comprises the steps of,

dividing the semiconductor integrated circuit into a plurality of wiring regions,

calculating routing congestion for respective wiring layers of the wiring regions, and

predicting the routes of respective wirings based on the routing congestions.

5. A design method as claimed in claim 1, wherein the adjacent wiring length predicting step comprises the steps of,

dividing the semiconductor integrated circuit into a plurality of wiring regions,

calculating routing congestion of respective wiring regions, and

predicting the adjacent wiring lengths based on the routing congestions.

6. A design method as claimed in claim 1, wherein the adjacent wiring length predicting step comprises the steps of,

dividing the semiconductor integrated circuit into a plurality of wiring regions to predict wiring lengths passing through respective wiring regions,

predicting expected values of adjacent wiring lengths of respective wiring regions based on routing congestions, and

predicting the adjacent wiring lengths of respective wiring regions based on predicted expected values of the adjacent wiring lengths.

7. A design method as claimed in claim 6, wherein the step of predicting expected values of adjacent wiring lengths of respective wiring regions based on routing congestions, includes the steps of calculating the expected values of adjacent wiring lengths as a function of routing congestion.

8. A design method as claimed in claim 6, wherein the step of predicting expected values of adjacent wiring lengths of respective wiring regions based on routing congestions, includes the step of calculating the expected values of adjacent wiring lengths as functions of routing congestion and adjacent wire spacing.

9. A design method as claimed in claim 6, wherein the adjacent wiring length predicting step comprises the steps of,

calculating wiring lengths and directions of respective wirings and wiring layers, for respective wiring regions through which wirings pass,

calculating the expected values of adjacent wiring lengths for respective wiring regions based on calculated routing congestion,

calculating predicted values of the adjacent wiring lengths for respective wiring regions, and

calculating a total sum of adjacent wiring lengths based on the predicted values of the adjacent wiring lengths.

10. A design method for a semiconductor integrated circuit, comprising:

a placing step of carrying out a layout placement of the semiconductor integrated circuit;

an interwiring capacitance calculating step of calculating capacitances between intersecting wirings of the semiconductor integrated circuit which has been subjected to the layout placement effected by the placing step; and

a re-placing step of carrying out a layout re-placement of the semiconductor integrated circuit based on calculation results;

wherein the interwiring capacitance calculating step comprises,

a wiring route predicting step of predicting routes of wirings of the semiconductor integrated circuit,

an intersecting wiring predicting step of predicting a number of the intersecting wirings based on predicted routes, and

an intersecting wiring capacitance calculating the step of calculating the capacitances between the intersecting wirings based on the number of the intersecting wirings being calculated.

11. A design method as claimed in claim 10, wherein the intersecting wiring predicting step comprises the steps of,

dividing the semiconductor integrated circuit into a plurality of wiring regions,

predicting wiring lengths passing through respective wiring regions,

calculating a number of wirings passing through respective sides of respective wiring regions,

calculating average numbers of wirings passing through vertical sides and horizontal sides of respective wiring regions,

calculating an intersecting number of wirings based on the average number of wirings, and

calculating a total intersecting number of wirings based on intersecting numbers of wirings being calculated for respective wiring regions.

12. A design method as claimed in claim 10, wherein the wiring route predicting step comprises the steps of,

dividing the semiconductor integrated circuit into a plurality of wiring regions,

calculating routing congestions of respective wiring regions, and

predicting the routes of respective wirings based on the routing congestions.

13. A design method as claimed in claim 10, wherein the wiring route predicting step comprises the steps of,

dividing the semiconductor integrated circuit into a plurality of wiring regions,

calculating routing congestions for respective sides of wiring regions, and

predicting the routes of respective wirings based on the routing congestions.

14. A design method as claimed in claim 10, wherein the wiring route predicting step comprises the steps of,

dividing the semiconductor integrated circuit into a plurality of wiring regions,

calculating routing congestion for respective wiring layers of the wiring regions, and

predicting the routes of respective wirings based on the routing congestions.

15. A design method as claimed in claim 10, wherein the re-placing step comprises the steps of,

carrying out a calculation of capacitances between adjacent wirings or capacitances between intersecting wirings of the semiconductor integrated circuit which has been subjected to the layout placement effected by the placing step,

calculating a critical path by calculating delay based on the capacitances between adjacent wirings or the capacitances between intersecting wirings of the semiconductor integrated circuit,

determining whether or not the critical path has satisfied specifications,

carrying out the layout re-placement of the semiconductor integrated circuit after generating path delay constraints unless the critical path has satisfied specifications,

carrying out the calculation of the capacitances between adjacent wirings of the semiconductor integrated circuit which has been subjected to the layout re-placement,

calculating the critical path by calculating delay based on the capacitances between adjacent wirings or the capacitances between intersecting wirings of the semiconductor integrated circuit which has been subjected to the layout re-placement, and

setting a lower limit value of net wiring distance unless the critical path has satisfied specifications, and then carrying out the layer re-placement of the semiconductor integrated circuit after generating the path delay constraints.

16. A computer-readable recording medium for recording a design program for a semiconductor integrated circuit, comprising:

a placing step of carrying out a layout placement of the semiconductor integrated circuit;

an interwiring capacitance calculating step of calculating capacitances between adjacent wirings or capacitances between intersecting wirings of the semiconductor integrated circuit which has been subjected to the layout design effected by the placing step; and

a re-placing step of carrying out a layout re-placement of the semiconductor integrated circuit based on calculation results;

wherein the interwiring capacitance calculating step comprises,

a wiring route predicting step of predicting routes of wirings of the semiconductor integrated circuit,

an adjacent wiring length predicting step of predicting adjacent wiring lengths based on predicted routes, and

an adjacent wiring capacitance calculating step of calculating the capacitances between the adjacent wirings based on the adjacent wiring lengths being calculated.

17. A method of manufacturing a semiconductor integrated circuit, comprising:

a placing step of carrying out a layout placement of the semiconductor integrated circuit;

an interwiring capacitance calculating step of calculating capacitances between adjacent wirings of capacitances between intersecting wirings of the semiconductor integrated circuit which has been subjected to the layout design effected by the placing step;

a re-placing step of carrying out a layout re-placement of the semiconductor integrated circuit based on calculation results;

a wiring step of carrying out a layout wiring of the semiconductor integrated circuit which has been subjected to the layout re-placement; and

a manufacturing step of manufacturing the semiconductor integrated circuit which has been subjected to the layout wiring;

wherein the interwiring capacitance calculating step comprises,

a wiring route predicting step of predicting routes of wirings of the semiconductor integrated circuit,

an adjacent wiring length predicting step of predicting adjacent wiring lengths based on predicted routes, and

an adjacent wiring capacitance calculating step of calculating the capacitances between the adjacent wirings based on the adjacent wiring lengths being calculated.

18. A design system for a semiconductor integrated circuit, comprising:

a placing unit for carrying out a layout placement of the semiconductor integrated circuit;

an interwiring capacitance calculator for calculating capacitances between adjacent wirings of the semiconductor integrated circuit which has been subjected to the layout design effected by the placing unit, comprising;

a wiring route predicting unit for predicting routes of wirings of the semiconductor integrated circuit,

an adjacent wiring length predicting unit for predicting adjacent wiring lengths based on predicted routes, and

an adjacent wiring capacitance calculator for calculating the capacitances between the adjacent wirings based on the adjacent wiring lengths being calculated;

a re-placing unit for carrying out a layout re-placement of the semiconductor integrated circuit based on calculation results, comprising;

a first circuit path calculating unit for calculating a critical path by calculating delay based on the capacitances between adjacent wirings or the capacitances between intersecting wirings of the semiconductor integrated circuit;

a determination unit for determining whether or not the critical path has satisfied specifications;

a layout re-placement unit for re-placing layout of the semiconductor integrated circuit after generating path delay constraints unless the critical path has satisfied specifications;

a second interwiring capacitance calculator for calculating of the capacitances between adjacent wirings of the semiconductor integrated circuit which has been subjected to the layout re-placement;

a second critical path calculator for calculating the critical path by calculating delay based on the capacitances between adjacent wirings or the capacitances between intersecting wirings of the semiconductor integrated circuit which has been subjected to the layout re-placement; and

a net wiring setting unit for setting a lower limit value of net wiring distance unless the critical path has satisfied specifications, and then carrying out the layout re-placement of semiconductor integrated circuit after generating the path delay constraints.

19. A design system for a semiconductor integrated circuit, comprising:

a logic design unit for carrying out a logic design of the semiconductor integrated circuit;

a placing unit for carrying out a layout placement of the semiconductor integrated circuit which has been subjected to the logic design;

an interwiring capacitance calculator for calculating capacitances between adjacent wirings of the semiconductor integrated circuit which has been subjected to the layout placement effected by the placing unit, comprising;

a wiring route predicting unit for predicting routes of wirings of the semiconductor integrated circuit,

an adjacent wiring length predicting unit for predicting adjacent wiring lengths based on predicted routes, and

an adjacent wiring capacitance calculator for calculating the capacitances between the adjacent wirings based on the adjacent wiring lengths being calculated;

a re-placing unit for carrying out a layout re-placement of the semiconductor integrated circuit based on calculation results comprising;

a first critical path calculating unit for calculating a critical path by calculating delay based on the capacitances between adjacent wirings or the capacitances between intersecting wirings of the semiconductor integrated circuit;

a determination unit for determining whether or not the critical path has satisfied specifications;

a layout re-placement unit for re-placing layout of the semiconductor integrated circuit after generating path delay constraints unless the critical path has satisfied specifications;

a second interwiring capacitance calculator for calculating of the capacitances between adjacent wirings of the semiconductor integrated circuit which has been subjected to the layout re-placement;

a second critical path calculator for calculating the critical path by calculating delay based on the capacitances between adjacent wirings or the capacitances between intersecting wirings of the semiconductor integrated circuit which has been subjected to the layout re-placement; and

a net wiring setting unit for setting a lower limit value of net wiring distance unless the critical path has satisfied specifications, and then carrying out the layout re-placement of semiconductor integrated circuit after generating the path delay constraints.

20. A design system for a semiconductor integrated circuit, comprising:

a placing unit for carrying out a layout placement of the semiconductor integrated circuit which has been subjected to the logic design;

an interwiring capacitance calculator for calculating capacitances between intersecting wirings of the semiconductor integrated circuit which has been subjected to the layout placement effected by the placing unit, comprising;

a wiring route predicting unit for predicting routes of wirings of the semiconductor integrated circuit,

an intersecting wiring predicting unit for predicting a number of the intersecting wirings based on predicted routes, and

an intersecting wiring capacitance calculating unit for calculating the capacitance between the intersecting wirings based on the number of intersecting wirings being calculated;

a re-placing unit for carrying out a layout re-placement of the semiconductor integrated circuit based on calculation results comprising;

a first critical path calculating unit for calculating a critical path by calculating delay based on the capacitances between intersecting wirings of the semiconductor integrated circuit;

a determination unit for determining whether or not the critical path has satisfied specifications;

a layout re-placement unit for re-placing layout of the semiconductor integrated circuit after generating path delay constraints unless the critical path has satisfied specifications;

a second interwiring capacitance calculator for calculating of the capacitances between intersecting wirings of the semiconductor integrated circuit which has been subjected to the layout re-placement;

a second critical path calculator for calculating the critical path by calculating delay based on the capacitances between intersecting wirings of the semiconductor integrated circuit which has been subjected to the layout re-placement; and

a net wiring setting unit for setting a lower limit value of net wiring distance unless the critical path has satisfied specifications, and then carrying out the layout re-placement of semiconductor integrated circuit after generating the path delay constraints.