×

Layout design method and system for an improved place and route

  • US 6,110,222 A
  • Filed: 05/13/1998
  • Issued: 08/29/2000
  • Est. Priority Date: 05/13/1997
  • Status: Expired due to Fees
First Claim
Patent Images

1. A design method for a semiconductor integrated circuit, comprising:

  • a placing step of carrying out a layout placement of the semiconductor integrated circuit;

    an interwiring capacitance calculating step of calculating capacitances between adjacent wirings of the semiconductor integrated circuit which has been subjected to the layout design effected by the placing step, comprising the steps of;

    a wiring route predicting step of predicting routes of wirings of the semiconductor integrated circuit;

    an adjacent wiring length predicting step of predicting adjacent wiring length based on predicted routes; and

    an adjacent wiring capacitance calculating step of calculating the capacitance between the adjacent wirings based on the adjacent wiring lengths being calculated;

    a re-placing step of carrying out a layout re-placement of the semiconductor integrated circuit based on calculation results, comprising the steps of;

    calculating a critical path by calculating delay based on the capacitances between adjacent wirings or the capacitances between intersecting wirings of the semiconductor integrated circuit,determining whether or not the critical path has satisfied specifications,carrying out the layout re-placement of the semiconductor integrated circuit after generating path delay constraints unless the critical path has satisfied specifications,carrying out the calculation of the capacitances between adjacent wirings of the semiconductor integrated circuit which has been subjected to the layout re-placement,calculating the critical path by calculating delay based on the capacitances between adjacent wirings or the capacitances between intersecting wirings of the semiconductor integrated circuit which has been subjected to the layout re-placement, andsetting a lower limit value of net wiring distance unless the critical path has satisfied specifications, and then carrying out the layout re-placement of the semiconductor integrated circuit after generating the path delay constraints.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×