Process for the fabrication of epitaxial layers of a compound semiconductor on monocrystal silicon and light-emitting diode fabricated therefrom

• US 6,110,277 A
• Filed: 04/14/1998
• Issued: 08/29/2000
• Est. Priority Date: 04/15/1997
• Status: Expired due to Fees

• Current Assignee: Vishay Semiconductor GmbH (Vishay Intertechnology Incorporated)
• Original Assignee: Temic Telefunken Microelectronic GmbH (Continental AG)
• Inventors: Braun, Matthias
• Primary Examiner(s): KUNEMUND, ROBERT M
• Application Number:
  US09/059,343
• Time in Patent Office: 868 Days
• Field of Search: 117/95, 117/94, 117/101, 117/97, 117/952
• US Class Current: 117/94
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01S 2304/12 Pendeo epitaxial lateral overgrowth [ELOG], e.g. for growing GaN based blue laser diodes
• CPC Class Codes: H01S 5/021 Silicon based substrates
• CPC Class Codes: H01S 5/32341 blue laser based on GaN or GaP

Abstract

A process for the fabrication on a monocrystal silicon substrate of epitaxial layers of a III-V nitride compound semi-conductor having the structure In_x Al_y Ga_1-x-y N (0≦x, 0≦y, x+y≦1). The process consists of the following steps. A parcel-like structure is created on the surface of a monocrystal silicon substrate. The silicon surface within the parcels is uncovered and the edges of the parcels are covered by a masking material. By means of epitaxial growth of the nitride compound semiconductor exclusively within the parcels on the silicon surface, local islands are created on whose edges the dislocations generated by the lattice mismatches are able to break down. Finally, components are fabricated in and on the parcels.

Claims

1. Process for the fabrication of epitaxial layers of a III-V nitride compound semi-conductor having the structure In_x Al_y Ga_1-x-y N (0≦

x, 0≦

y, x+y≦

1) on a substrate made up of monocrystal silicon, such process comprising the following steps;

providing the monocrystal silicon substrate;

creating a parcel-like structure on the surface of the substrate, such that the silicon surface in the parcel is uncovered and the edges of the parcels are covered by a masking material;

growing a nucleation layer on the silicon surface in the parcels; and

epitaxially growing the nitride compound semiconductor exclusively in the parcels on the nucleation layer.

2. Process as claimed in claim 1, wherein silicon dioxide SiO₂ or silicon oxinitride SiON deposited on the surface of the substrate is used as masking material.

3. Process as claimed in claim 1, wherein silicon dioxide SiO₂ grown on the surface of the substrate is used as masking material.

4. Process as claimed in claim 1, wherein the nucleation layer contains one of arsenic nitride AsN and nitrogen N.

5. Process as claimed in claim 1, wherein a lattice matching region comprising several part layers is epitaxially grown in the parcels on the on the nucleation layer.

6. Process as claimed in claim 5, wherein the nitride compound semiconductor epitaxially grown on the lattice matching region contains an active region with a p/n or an n/p junction.

7. Process as claimed in claim 6, wherein the active region consists of mono-layers or a superlattice for the setting of the component-relevant parameters.

8. Process as claimed in one of the claim 1, wherein a semiconductor layer having a lower bandgap than that of the active region and which enhances the contact properties is grown on the active region.

9. Process as claimed in claim 8, wherein the contact layer is locally removed by of selective etching.

10. Process as claimed in claim 1, wherein the substrate is doped.

11. Process as claimed in claim 1, wherein a metallic layer is applied to the rear side of the substrate for contacting purposes.

12. Process as claimed in claim 1, wherein the semiconductor layer arrangement grown on the silicon surface in the parcels is coated with a passivation layer.

13. Process as claimed in claim 1, wherein the epitaxial layers are used for the fabrication of an LED or a diode laser.