Trench contact process

• US 6,110,799 A
• Filed: 06/30/1997
• Issued: 08/29/2000
• Est. Priority Date: 06/30/1997
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Inventors: Huang, Qin
• Primary Examiner(s): Chaudhari, Chandra
• Assistant Examiner(s): Blum, David S
• Application Number:
  US08/885,879
• Time in Patent Office: 1,156 Days
• Field of Search: 438/440, 438/221, 438/223, 438/294, 438/295, 438/296, 438/237, 438/268, 438/293, 438/315, 438/316, 438/336, 438/337, 438/348, 438/355, 438/256, 438/329, 438/330, 438/331, 257/330, 257/331, 257/377, 257/325-332
• US Class Current: 438/430
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench process for establishing a contact for a semiconductor device with trenches such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs which reduces the number of masks and eliminates the need for lateral diffusion into the trench channel region. Improved control of the parasitic transistor in the trench MOSFET is also achieved. The cell size/pitch is reduced relative to conventional processes which require source block and P+ masks.

Claims

1. A method of manufacturing a semiconductor device using a trench for conductor formation comprising the steps of:

(a) providing a semiconductor of a first polarity;

(b) providing a first mask for a surface of the semiconductor to thereby define an active region on the semiconductor;

(c) implanting an impurity of a second semiconductor polarity in the surface exposed by the active region mask and annealing the semiconductor to drive in the second polarity semiconductor impurity to thereby create a second polarity region in the semiconductor;

(d) implanting an impurity of the first polarity in the channel region and annealing the semiconductor to drive the first polarity impurity into the channel region to thereby create a first polarity surface region adjacent the surface of the semiconductor;

(e) providing a second mask defining a trench region on the exposed surface;

(f) forming first and second spaced apart trenches extending downwardly through the second mask, the source region and the channel region into the semiconductor;

(g) forming a gate oxide layer over the exposed upper surface of the semiconductor and the walls and bottom of the first and second trenches;

(h) providing a layer of polysilicon over the gate oxide layer completely filling the first and second trenches;

(i) providing a third mask to thereby define an area larger than the active region to protect the polysilicon layer for later gate contact;

(j) etching back the polysilicon layer overlying the gate oxide in the area not protected by the third mask to leave the trenches filled with polysilicon;

(k) forming a layer of BPSG over the exposed surface of the semiconductor, gate oxide layer and first and second trenches;

(l) forming a fourth mask over the BPSG layer defining a third trench intermediate the first and second trenches;

(m) doping the semiconductor at the bottom of the third trench with an impurity of the second polarity to thereby create a density greater than the density of the impurity of the second polarity in the channel region to thereby create a high concentration region adjacent the bottom of the third trench; and

(n) forming a metal layer overlying both the BPSG layer and the area of the third trench to thereby establish electrical contacts with the first polarity layer and the second polarity layer.

3. The method of claim 1, wherein the high concentration region is formed by annealing the semiconductor to drive the impurity of the second polarity into the semiconductor.

4. The method of claim 1, wherein the high concentration region is formed by diffusing the impurity into the semiconductor.

2. The method of reducing the cell pitch of an integrated circuit having a horizontal PN junction comprising the steps of:

(a) forming a pair of spaced trenches of a first electrically conducting material surrounded by insulation in said integrated circuit;

(b) forming a third trench between said pair of spaced trenches; and

,

(c) filling said third trench with a metal to establish a metal contact with the semiconductor on both components of the PN junction along a generally vertical plane.

5. The method of claim 2, furthering including the step of diffusing a dopant from the bottom of said third trench into the semiconductor before the step of filling said third trench with a metal to thereby form a buried layer of high dopant concentration in contact with one of the components of the PN junction.

6. The method of claim 5 wherein the metal in the third trench contacts the buried layer as well as both components of the PN junction.

7. A method of creating a semiconductor structure with a horizontal PN junction where the location of the FET break down occurs at the point other than said horizontal PN junction comprising the steps of:

(a) forming a pair of spaced trenches of a first electrically conducting material surrounded by insulation in said semiconductor structure;

(b) forming a third trench between said pair of spaced trenches; and

,

(c) diffusing a dopant from the bottom of said third trench into the semiconductor to thereby form a layer of high dopant concentration; and

,

(d) filling said third trench with a metal to establish a metal contact with said semiconductor structure on both components of the PN junction and with said layer of high dopant concentration along a generally vertical plane.

8. The method of claim 7 wherein the layer of high dopant concentration is in contact with the component of said PN junction of the same conductivity.