Method and apparatus for in situ anneal during ion implant

• US 6,111,260 A
• Filed: 06/10/1997
• Issued: 08/29/2000
• Est. Priority Date: 06/10/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Dawson, Robert, Fulford, Jr., H. Jim, Gardner, Mark I., Hause, Frederick N., Michael, Mark W., Moore, Bradley T., Wristers, Derick J.
• Primary Examiner(s): BERMAN, JACK I
• Application Number:
  US08/872,258
• Time in Patent Office: 1,176 Days
• Field of Search: 250/492.21, 250/443.11
• US Class Current: 250/492.21
• CPC Class Codes: H01J 2237/316 Changing physical properties
• CPC Class Codes: H01J 37/3171 for ion implantation plasma immersion ion implantation H01J37/32412

Abstract

During a semiconductor substrate ion implant process thermal energy is supplied to raise the temperature of the semiconductor wafer. The increased temperature of the semiconductor wafer during implantation acts to anneal the implanted impurities or dopants in the wafer, reducing impurity diffusion and reducing the number of fabrication process steps. An ion implant device includes an end station that is adapted for application and control of thermal energy to the end station for raising the temperature of a semiconductor substrate wafer during implantation. The adapted end station includes a heating element for heating the semiconductor substrate wafer, a thermocouple for sensing the temperature of the semiconductor substrate wafer, and a controller for monitoring the sensed temperature and controlling the thermal energy applied to the semiconductor substrate wafer by the heating element. An ion implant device including a system for applying and controlling thermal energy applied to a semiconductor substrate wafer during ion implantation raises the temperature of the wafer to a temperature that is sufficient to activate impurities within the semiconductor substrate wafer when an ion beam is implanting ions to the wafer, but the temperature is insufficient to activate impurities when the ion beam is inactive.

Claims

1. A semiconductor processing apparatus for processing a substrate wafer comprising:

a feed source for supplying implant ions in the form of a feed gas;

an ion source coupled to the feed source for ionizing the feed gas;

an ion extracting and analyzing device coupled to the ion source for selecting a predetermined ion species from the ionized feed gas according to mass;

an acceleration tube coupled to the ion extracting and analyzing device for creating an acceleration field to increase the ion energy of the selected ion species and for creating and focusing an ion beam;

a beam chamber coupled to the acceleration tube for passing the ion beam to the substrate wafer;

a scanner coupled to the beam chamber for directing the ion beam through the beam chamber and scanning the ion beam across a surface of the substrate wafer;

an end station including an area-defining aperture, a Faraday cup and current integrator, and a wafer holder for loading, holding and positioning the substrate wafer;

a vacuum system coupled for evacuating the end station, the beam chamber and the acceleration tube;

a heating unit coupled to the end station for generating a thermal energy supplied to the substrate wafer during application of the ion beam to the substrate wafer;

a controller coupled to the feed source, the ion source, and the ion extracting and analyzing device, the scanner, the vacuum system, and the heating unit for controlling the composition and energy of the ion beam, the physical positioning and timing of the scanner, the pressure within the end station, the beam chamber and the acceleration tube, and the thermal energy supplied to the substrate wafer; and

an operating logic coupled to the controller for defining functional operations of the controller, the operating logic including a control sequence for simultaneously supplying a predetermined thermal energy to the substrate wafer and generating an ion beam impinging on the substrate wafer, and the operating logic including a control sequence for degassing the substrate wafer by controlling the heating unit to generate a flash heat preceding the step of simultaneously supplying a predetermined thermal energy to the substrate wafer and generating an ion beam impinging on the substrate wafer.

2. A semiconductor processing apparatus according to claim 1 further comprising:

a plasma etch system including an end chamber coupled to the end station, the vacuum system, a gas supply, and a power supply.

3. A semiconductor processing apparatus according to claim 2 further comprising:

a controller coupled to the feed source, the ion source, and the ion extracting and analyzing device, the scanner, the vacuum system, and the heating unit for controlling the composition and energy of the ion beam, the physical positioning and timing of the scanner, the pressure within the end station, the beam chamber and the acceleration tube, and the thermal energy supplied to the substrate wafer.

4. A semiconductor processing apparatus according to claim 3 further comprising:

an operating logic coupled to the controller for defining functional operations of the controller, the operating logic including a control sequence for simultaneously supplying a predetermined thermal energy to the substrate wafer and generating an ion beam impinging on the substrate wafer.

5. A semiconductor processing apparatus according to claim 4 further comprising:

an operating logic coupled to the controller for defining functional operations of the controller, the operating logic including a control sequence for degassing the substrate wafer by controlling the plasma etch system to bombard the substrate wafer with plasma preceding the step of simultaneously supplying a predetermined thermal energy to the substrate wafer and generating an ion beam impinging on the substrate wafer.

6. A semiconductor processing apparatus for processing a substrate wafer comprising:

an ion implant device including an end chamber for holding the substrate wafer under process, the ion implant device for generating an ion beam for implanting ions in the substrate wafer;

a thermal processing unit coupled to the end chamber for generating a thermal energy supplied to the substrate wafer during application of the ion beam to the substrate wafer; and

a controller coupled to the ion implant device and the thermal processing unit for controlling the composition and energy of the ion beam, the physical positioning and timing of the ion beam in application to the substrate wafer, and the thermal energy supplied to the substrate wafer;

an operating logic coupled to the controller for defining functional operations of the controller, the operating logic including a control sequence for simultaneously supplying a predetermined thermal energy to the substrate wafer and generating an ion beam impinging on the substrate wafer, the operating logic including a control sequence for degassing the substrate wafer by controlling the heating unit to generate a flash heat preceding the step of simultaneously supplying a predetermined thermal energy to the substrate wafer and generating an ion beam impinging on the substrate wafer.

7. A semiconductor processing apparatus according to claim 6 further comprising:

a lamp heating device coupled to the thermal processing unit for generating a thermal energy.

8. A semiconductor processing apparatus according to claim 6 further comprising:

a resistance heating device coupled to the thermal processing unit for generating a thermal energy.

9. A semiconductor processing apparatus according to claim 6 further comprising:

an operating logic coupled to the controller for defining functional operations of the controller, the operating logic including a control sequence for simultaneously supplying a predetermined thermal energy to the substrate wafer and generating an ion beam impinging on the substrate wafer.

10. A semiconductor processing apparatus according to claim 6 further comprising:

an operating logic coupled to the controller for defining functional operations of the controller, the operating logic including a control sequence for degassing the substrate wafer by controlling the heating unit to generate a flash heat preceding the step of simultaneously supplying a predetermined thermal energy to the substrate wafer and generating an ion beam impinging on the substrate wafer.

11. A semiconductor processing apparatus according to claim 6 further comprising:

a plasma etch system including the end chamber, a vacuum system, a gas supply, and a power supply.

12. A semiconductor processing apparatus according to claim 11 further comprising:

an operating logic coupled to the controller for defining functional operations of the controller, the operating logic including a control sequence for simultaneously supplying a predetermined thermal energy to the substrate wafer and generating an ion beam impinging on the substrate wafer.

13. A semiconductor processing apparatus according to claim 12 further comprising:

an operating logic coupled to the controller for defining functional operations of the controller, the operating logic including a control sequence for degassing the substrate wafer by controlling the plasma etch system to bombard the substrate wafer with plasma preceding the step of simultaneously supplying a predetermined thermal energy to the substrate wafer and generating an ion beam impinging on the substrate wafer.

14. A method of processing a substrate wafer comprising the steps of:

generating an ion beam impinging on the substrate wafer, the ion beam inherently producing an ion beam inherent thermal energy to the substrate wafer; and

supplying a predetermined thermal energy to the substrate wafer using a heating unit simultaneous with the generation of the ion beam impinging on the substrate wafer, the predetermined thermal energy and the ion beam inherent thermal energy in combination supplying a thermal energy sufficient to anneal the substrate wafer; and

degassing the substrate wafer by generating a flash heat using the heating unit preceding the steps of simultaneously supplying a predetermined thermal energy to the substrate wafer and generating an ion beam impinging on the substrate wafer.

15. A method of processing a substrate wafer according to claim 14 further comprising the step of:

degassing the substrate wafer by bombarding the substrate wafer with plasma preceding the step of simultaneously supplying a predetermined thermal energy to the substrate wafer and generating an ion beam impinging on the substrate wafer.

16. A method of processing a substrate wafer according to claim 14 further comprising the step of:

supplying a predetermined thermal energy to the substrate wafer using a lamp heating device.

17. A method of processing a substrate wafer according to claim 14 further comprising the step of

supplying a predetermined thermal energy to the substrate wafer using a resistance heating device.

18. A semiconductor processing apparatus for processing a substrate wafer comprising:

an ion implant device including an end chamber for holding the substrate wafer under process, the ion implant device for generating an ion beam for implanting ions in the substrate wafer;

a thermal processing unit coupled to the end chamber for generating a thermal energy supplied to the substrate wafer during application of the ion beam to the substrate wafer;

a controller coupled to the ion implant device and the thermal processing unit for controlling the composition and energy of the ion beam, the physical positioning and timing of the ion beam in application to the substrate wafer, and the thermal energy supplied to the substrate wafer; and

an operating logic coupled to the controller for defining functional operations of the controller, the operating logic including a control sequence for simultaneously supplying a predetermined thermal energy to the substrate wafer and generating an ion beam impinging on the substrate wafer to a change a portion of the substrate wafer from a crystalline structure to an amorphous structure.

19. A method of processing a substrate wafer comprising the steps of:

generating an ion beam impinging on the substrate wafer, the ion beam inherently producing an ion beam inherent thermal energy to the substrate wafer; and

supplying a predetermined thermal energy to the substrate wafer simultaneous with the generation of the ion beam impinging on the substrate wafer, the predetermined thermal energy and the ion beam inherent thermal energy in combination supplying a thermal energy sufficient to anneal the substrate wafer and sufficient to change a portion of the substrate wafer from a crystalline structure to an amorphous structure.