CMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed silicon germanium layer where germanium is between 25 and 50%, and another intrinsic silicon layer

• US 6,111,267 A
• Filed: 05/04/1998
• Issued: 08/29/2000
• Est. Priority Date: 05/13/1997
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Fischer, Hermann, Hofmann, Franz
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Brewster, William M.
• Application Number:
  US09/071,153
• Time in Patent Office: 848 Days
• Field of Search: 257/19, 257/280, 257/281, 257/192, 257/274, 257/69, 257/197, 257/616
• US Class Current: 257/19
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/8256 the substrate being a semiconductor, using technologies not covered by one of groups H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252 and H01L21/8254 H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

An integrated CMOS circuit, and method for producing same, including a semiconductor substrate having a p-channel MOS transistor and an n-channel MOS transistor formed therein and having a first silicon layer, a stressed Si_1-x Ge_x layer and a second silicon layer which are preferably grown by selective epitaxy. In an ON state, a buried channel is formed in the stressed Si_1-x Ge_x layer in the p-channel MOS transistor and a surface channel is formed in the second silicon layer in the n-channel MOS transistor.

Claims

1. An integrated CMOS circuit, comprising a semiconductor substrate including at least a first silicon layer having a thickness of between 30 nm and 70 nm, a stressed Si_1-x Ge_x layer having a thickness of between 5 nm and 10 nm and a germanium content of between 50 atomic percent and 25 atomic percent and a second silicon layer having a thickness of between 5 nm and 12 nm, wherein the stressed Si_1-x Ge_x layer has a lattice constant which is substantially equal to respective lattice constants of both the first silicon layer and the second silicon layer, wherein a p-channel MOS transistor and an n-channel MOS transistor are formed in the semiconductor substrate wherein a conductive channel is formed within the Si_1-x Ge_x layer in the p-channel MOS transistor, and wherein a conductive channel is formed in the second silicon layer in the n-channel MOS transistor.