Radially-increasing core power bus grid architecture

• US 6,111,310 A
• Filed: 09/30/1998
• Issued: 08/29/2000
• Est. Priority Date: 09/30/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Schultz, Richard T.
• Primary Examiner(s): Hardy, David
• Assistant Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US09/163,683
• Time in Patent Office: 699 Days
• Field of Search: 257/691, 257/692, 257/723, 257/666, 257/735, 438/611, 438/735
• US Class Current: 257/691
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A power bus grid architecture for an integrated circuit including a plurality of main bars assembled along the perimeter of the grid and a plurality of bus bars assembled within the perimeter of the grid. The bus bars are each composed of a plurality of segments with each segment having a substantially constant width. Each segment on certain bus bars has a different width from the next adjacent segment. The width of a particular segment is determined by the distance of the segment from the nearest main power bar. Because the current flow through the segments nearest to the main power bar tends to be greater than the current flow through the segments further from the main power bar, the segments nearest to the main power bar can be made much wider than the segments furthest from the main power bar without significant deleterious effects to the circuit from voltage drops or electromigration.

Claims

1. An integrated circuit, comprising:

a plurality of circuits provided on a substrate of semiconductor material; and

a power bus grid in electrical communication with the plurality of circuits, wherein the grid has a plurality of main bars and bus bars, the bus bars having a cross-sectional area that varies as a function of the distance from the nearest connection to a main bar.

2. An integrated circuit as defined in claim 1, wherein the cross-sectional area of the bus bars decreases as the distance from the nearest main bar increases.

3. An integrated circuit as defined in claim 1, wherein the main bars are connected together in a rectangular shape proximate to a perimeter of the integrated circuit.

4. An integrated circuit as defined in claim 1, wherein the power bus grid further includes multiple layers of grids with a plurality of main bars and bus bars, the bus bars having a cross-sectional area that varies as a function of the distance from the nearest connection to a main bar.

5. An integrated circuit as defined in claim 1, wherein the main bars have a cross-sectional area that is substantially equal to or greater than the cross-sectional area of the bus bars.

6. An integrated circuit as defined in claim 1, wherein at least a portion of the power bus grid overlays the plurality of circuits.

7. An integrated circuit as defined in claim 2, wherein the cross-sectional area of the bus bars is substantially constant between connections to other bus bars.

8. An integrated circuit as defined in claim 7, wherein the main bars are connected together in a rectangular shape proximate to a perimeter of the integrated circuit.

9. An integrated circuit as defined in claim 8, wherein the cross-sectional area of the bus bars is relatively smaller at a center of the integrated circuit than near the main bars.

10. An integrated circuit as defined in claim 4, wherein the power bus grid is attachable to a power supply that supplies a supply voltage between a pair of conductors, at least one of the multiple layers of the power bus grid being attachable to a first one of the pair of conductors and at least one other of the multiple layers of the power bus grid being attachable to the other of the pair of conductors, to supply the supply voltage to the plurality of circuits.

11. An integrated circuit, comprising:

a plurality of circuits provided on a substrate of semiconductor material; and

a power bus grid in electrical communication with the plurality of circuits, wherein the grid has a plurality of main bars and bus bars, the bus bars having portions that are relatively closer to the main bars and portions that are relatively further from the main bars, wherein the closer portions have a cross-sectional area that is relatively greater than a cross-sectional area of the further portions.

12. An integrated circuit, comprising:

a plurality of circuits provided on a substrate of semiconductor material; and

a power bus grid including multiple, spaced-apart, substantially-planar layers, with each layer including a generally rectangular arrangement of main bars connectable to a power supply, each layer also including a plurality of bus bars arranged in the shape of a grid, wherein each bus bar includes a plurality of segments, the bus bars having segments that are relatively closer to the main bars and segments that are relatively further from the main bars, wherein the closer segments have a cross-sectional area that is relatively greater than a cross-sectional area of the further segments.