Very low power logic circuit family with enhanced noise immunity

• US 6,111,425 A
• Filed: 10/15/1998
• Issued: 08/29/2000
• Est. Priority Date: 10/15/1998
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude L., Tonti, William R., Houghton, Russell J., Pricer, Wilbur D.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, DON P
• Application Number:
  US09/173,436
• Time in Patent Office: 684 Days
• Field of Search: 326/21-23, 326/26, 326/27, 326/83, 327/55, 327/67
• US Class Current: 326/21
• CPC Class Codes: H03K 19/1738 using cascode switch logic [CSL] or cascode emitter coupled logic [CECL]
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A very low power logic circuit family which advantageously provides 1) retained high performance, 2) significantly reduced power dissipation, and 3) enhanced noise immunity. In a first set of embodiments, dual rail complementary logic signals are utilized to improve circuit immunity to external noise and to reduce noise generated by the logic circuit itself. A receiver portion of the present invention comprises two input FETs having cross coupling of the two gates to the two sources. In one preferred embodiment, both receiver and driver portions are connected in a repeater with all N channel drivers. A second set of embodiments have a single sided input in an unbalanced receiver comprising cross coupled source to gate N channel and cross coupled drain to gate P channel output transistors.

Claims

1. A low power digital circuit with enhanced noise immunity comprising:

an input for receiving differential input signals, the input comprising a first pair of first type input FETs cross-coupled gate-to-source, with each FET receiving one of the differential signals at its source;

a pair of a second type output FETs cross-coupled gate-to-drain, with the second type FETs having their sources directly coupled to a first voltage terminal, and each second type FET having its drain directly coupled to a separate one of the drains of the first type FET; and

a first output at a first node between one of the first type FETs drains and one of the second type FETs drains, providing a first output signal having a higher voltage swing than the differential input signals.

2. A digital circuit as in claim 1, further comprising:

a second output at a second node between another of the first type FET drains and another of the second type FET drains, providing a second output signal complementary to the first output signal.

3. A digital circuit as in claim 2, further comprising:

a second pair of first type FETs coupled in series between a second voltage terminal and a third voltage terminal, a voltage at the second voltage terminal being intermediate between a voltage at the first voltage terminal and a voltage at the third voltage terminal, wherein the second pair of first type FETs are each gate-coupled to one of the first and second nodes; and

a third output at a third node between the second pair of first type FETs.

4. A digital circuit as in claim 3, wherein the first pair of first type FETs are low Vt FETs.

5. A digital circuit as in claim 4, wherein the first type FETs are N channel FETs, and the second type FETs are P channel FETs.

6. A digital circuit as in claim 1, wherein the first pair of first type FETs are low Vt FETs.

7. A digital circuit as in claim 1, wherein the first type FETs are N channel FETs, and the second type FETs are P channel FETs.

8. A digital circuit as in claim 1, wherein the two input FETs are cross coupled source to back gate.

9. A digital circuit as in claim 1, wherein the two input FETs are cross coupled source to both front and back gates.

10. A digital circuit as in claim 2, wherein each of the first and second outputs are directed to a CMOS inverter/driver.

11. A digital circuit as in claim 2, wherein each of the first and second outputs are directed to an all N channel logic gate which can be either an OR/NOR or an AND/NAND combination by reordering the input true complement variables.

12. A digital circuit as in claim 1, in a Cascode Voltage Switch.

13. A low power digital circuit with enhanced noise immunity comprising:

an input for receiving a single sided input signal, the input comprising a pair of first type input FETs cross-coupled gate-to-source;

a pair of a second type output FETs cross-coupled gate-to-drain, with the second type output FETs having their drains directly coupled to a first voltage terminal, and each second type FET having its source directly coupled to a separate one of the drains of the first type FET;

an output at a node between one of the first type FETs drains and one of the second type FETs sources, providing output signal having a higher voltage swing than the differential input signals;

an input logic signal is compared to a reference potential (Vref) which is one half of the Vsh supply.

14. A digital circuit as in claim 13, wherein an in phase signal generated by the receiver achieves the full logic level swing down to ground potential, and the out of phase signal swings only from vdd to Vref, not all the way to ground.

15. A digital circuit as in claim 13, wherein the first type FETs are N channel FETs, and the second type FETs are P channel FETs.

16. A digital circuit as in claim 13, wherein the in phase signal is an input to a CMOS inverter.

17. A digital circuit as in claim 13, in a CMOS NAND gate.

18. A digital circuit as in claim 13, comprising an NMOS inverter/driver coupled to NMOS logic circuitry.