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Very low power logic circuit family with enhanced noise immunity

  • US 6,111,425 A
  • Filed: 10/15/1998
  • Issued: 08/29/2000
  • Est. Priority Date: 10/15/1998
  • Status: Expired due to Term
First Claim
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1. A low power digital circuit with enhanced noise immunity comprising:

  • an input for receiving differential input signals, the input comprising a first pair of first type input FETs cross-coupled gate-to-source, with each FET receiving one of the differential signals at its source;

    a pair of a second type output FETs cross-coupled gate-to-drain, with the second type FETs having their sources directly coupled to a first voltage terminal, and each second type FET having its drain directly coupled to a separate one of the drains of the first type FET; and

    a first output at a first node between one of the first type FETs drains and one of the second type FETs drains, providing a first output signal having a higher voltage swing than the differential input signals.

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