Method for controlling delays in silicon on insulator circuits
First Claim
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1. A semiconductor integrated circuit device, comprising:
- a static circuit having a plurality of p-channel and n-channel transistors, each of said transistors has a floating body, wherein said static circuit includes an input and an output;
a rise delay control circuit coupled to a floating body of said p-channel transistors in said static circuit for selectively controlling delays of a rising output signal at said output of said static circuit via a rise delay signal; and
a fall delay control circuit coupled to a floating body of said n-channel transistors in said static circuit for selectively controlling delays of a falling output signal at said output of said static circuit via a fall delay signal;
wherein each of said rise delay control circuit and said fall delay control circuit includes a transistor pair.
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Abstract
A method for controlling delays in silicon on insulator circuits is disclosed. A semiconductor integrated circuit device comprises a first circuit and a second circuit. The first circuit includes multiple transistors, some of which have a floating body. In addition, the first circuit includes an input and an output. The second circuit is selectively coupled to a floating body of some of the transistors in the first circuit in order to control the delay of the output of the first circuit.
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Citations
10 Claims
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1. A semiconductor integrated circuit device, comprising:
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a static circuit having a plurality of p-channel and n-channel transistors, each of said transistors has a floating body, wherein said static circuit includes an input and an output; a rise delay control circuit coupled to a floating body of said p-channel transistors in said static circuit for selectively controlling delays of a rising output signal at said output of said static circuit via a rise delay signal; and a fall delay control circuit coupled to a floating body of said n-channel transistors in said static circuit for selectively controlling delays of a falling output signal at said output of said static circuit via a fall delay signal;
wherein each of said rise delay control circuit and said fall delay control circuit includes a transistor pair. - View Dependent Claims (2, 3)
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4. A semiconductor integrated circuit device, comprising:
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a dynamic circuit having a precharge transistor and an isolation transistor, each of said transistors has a floating body and a gate connected to a clock signal, wherein said dynamic circuit includes a logic circuit connected in series between the precharge transistor and the isolation transistor;
wherein the logic circuit has an output and at least one input;a rise delay control circuit coupled only to a floating body of said precharge transistor in said dynamic circuit for selectively controlling delays of a rising output signal at said output of said dynamic circuit via a rise delay signal; and a fall delay control circuit coupled only to a floating body of said isolation transistor in said dynamic circuit for selectively controlling delays of a falling output signal at said output of said dynamic circuit via a fall delay signal;
wherein each of said rise delay control circuit and said fall delay control circuit includes a transistor pair. - View Dependent Claims (5, 6, 7)
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8. A semiconductor integrated circuit device, comprising:
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a transmission gate circuit having a p-channel transistor and an n-channel transistor connected in parallel, each of said transistors has a floating body, wherein said transmission gate circuit has an input and an output; a rise delay control circuit coupled to a floating body of said p-channel transistor in said transmission gate circuit for selectively controlling delays of a rising output signal at said output of said transmission gate circuit via a rise delay signal; and a fall delay control circuit coupled to a floating body of said n-channel transistor in said transmission gate circuit for selectively controlling delays of a falling output signal at said output of said transmission gate circuit via a fall delay signal;
wherein each of said rise delay control circuit and said fall delay control circuit includes a transistor pair. - View Dependent Claims (9, 10)
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Specification