Method to improve the jitter of high frequency phase locked loops used in read channels

• US 6,111,712 A
• Filed: 03/06/1998
• Issued: 08/29/2000
• Est. Priority Date: 03/06/1998
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Vishakhadatta, G. Diwakar, Hein, Jerrell P.
• Primary Examiner(s): Kim, W. Chris
• Application Number:
  US09/036,608
• Time in Patent Office: 907 Days
• Field of Search: 360/51, 360/46, 369/59, 331/2, 331/50
• US Class Current: 360/51
• CPC Class Codes: G11B 19/247 using electrical means
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

A system and method is provided to improve the jitter performance of high frequency synthesizers used in read/write channel circuits. The frequency synthesizer is implemented with multiple phase locked loops arranged in a cascaded fashion to increase the update rates at which the cascaded loops operate at for a given frequency resolution of the synthesizer. The cascaded or staged phase locked loops may be utilized for generating read, write, and servo clocks for a read/write channel circuit. The cascaded phase locked loops may also be arranged such that one or more stages are shared to generate the read, write or servo clocks.

Claims

1. A data channel circuit for processing data of a data storage medium, comprising:

at least a first circuit coupled to at least a first clock signal, the first circuit processing data to be read from or written to the data storage medium;

at least a second circuit coupled to at least a second clock signal, the second circuit processing data to be read from or written to the data storage medium; and

a frequency synthesizer generating the first clock signal and the second clock signal, the frequency synthesizer comprising,

a first phase locked loop circuit, the first phase locked loop circuit receiving a reference clock signal and having a first phase locked loop output signal,

a second phase locked loop circuit, the second phase locked loop circuit receiving as an input the first phase locked loop output signal and the second phase locked loop providing as an output the first clock signal; and

a third phase locked loop circuit, the third phase locked loop circuit receiving as an input the first phase locked loop output signal and providing as an output the second clock signal,

wherein the first clock signal is at least one of a read clock signal, a write clock signal or a servo clock signal, and the second clock is at least one of a read clock signal, a write clock signal or a servo clock signal, and wherein both the read clock signal and the write clock are provided from either the second or third phase locked loop circuits.

2. The data channel circuit of claim 1, frequency synthesizer being programmable to provide the first clock signal with a frequency range of at least approximately 100 MHz with a frequency resolution of approximately 0.4% or less.

3. The data channel circuit of claim 2, the frequency of the first phase locked loop output signal being approximately equal to or greater than the frequency of the first clock signal.

4. The data channel circuit of claim 1, the first clock signal being a read and write clock signal and the second clock being a servo clock signal.

5. The data channel circuit of claim 1,

wherein the second circuit processes data to be read from or written to the data storage medium.

6. The data channel circuit of claim 1, the frequency of the first phase locked loop output signal being approximately equal to or greater than the frequency of the first clock signal.

7. The data channel circuit of claim 6, the frequency of the first clock signal being programmable.

8. A data channel circuit having a frequency synthesizer, comprising:

a first stage phase locked loop circuit having a first output signal; and

a plurality of second stage phase locked loop circuits, each of the second stage phase locked loop circuits having separate second output signals, an input of each second stage phase locked loop circuit being the first output signal, the second output signals including at least a write clock signal and a read clock signal,

the frequency of the first output signal being equal to or greater than the frequency of at least one of the second output signals.

9. The data channel circuit of claim 8, the frequency of the second output signal being programmable.

10. The data channel circuit of claim 8, the frequency synthesizer being programmable to provide the second output signal with a frequency range of at least approximately 100 MHz with a frequency resolution of approximately 0.4% or less.

11. A method of operating a data channel circuit for processing data of a data storage medium, comprising:

processing the data within the data channel circuit with clocked circuitry;

generating at least one clock signal with at least a first stage and a second stage phase locked loop circuit, the phase locked loop circuits being cascaded, the first stage phase locked loop circuit receiving a reference clock signal as an input, the output of the first stage phase locked loop circuit being provided to the input of the second stage phase locked loop circuit, the at least one clock signal coupled to the output of the second stage phase locked loop circuit; and

cascading a plurality of second stage phase locked loop circuit with the first stage phase locked loop circuits, the outputs of the plurality of second stage phase locked loop circuits providing separate clock signals for clocking read and write circuitry.

12. The method of claim 11, the output of the first stage phase locked loop being at a frequency greater than the reference clock signal and the output of at least one of the second stage phase locked loops being at a frequency less than or equal to the frequency of the first phase locked loop.

13. The method of claim 12, further comprising programming at least one of the phase locked loop circuits by adjusting phase locked loop divisors.

14. A data storage system comprising:

a data storage medium;

at least two data channel circuits connected to the data storage medium, the data channel circuits including at least two circuits selected from the group comprised of read circuits, write circuits and servo circuits; and

a frequency synthesizer within the data channel circuitry, the frequency synthesizer providing at least two clock signals for clocking the at least two data channel circuits, the frequency synthesizer comprising,

at least a first phase locked loop, a second phase locked loop, and a third phase locked loop, the output of the first phase locked loop being provided as an input to the second phase locked loop and as an input to the third phase locked loop, one of the at least two clock signals being coupled to the output of the second phase locked loop and another of the at least two clock signals being coupled to the output of the third phase locked loop, the two clock signals providing at least a write and read clock signal.

15. The data storage system of claim 14, the frequency of the output of the first phase locked loop being approximately equal to or greater than the frequency of the at least one clock signal.

16. The data channel circuit of claim 15, the frequency of the output of the first phase locked loop and the frequency of the at least one clock signal being programmable.

17. A method of operating a programmable frequency synthesizer within a data channel circuit, comprising:

cascading in series at least a first and a second phase locked loop;

providing a reference clock signal to the input of the first phase locked loop;

providing the output of the first phase locked loop to the input of the second phase locked loop;

providing the output of the first phase locked loop to the input of a third phase locked loop, read and write clocks being provided from one or both of the second or third phase locked loops;

programming the frequency synthesizer by adjusting loop divisors of at least one of the first and second phase locked loops to provide a frequency synthesizer output over a wide frequency range;

improving the jitter performance of the frequency synthesizer for a given frequency resolution by maintaining the frequency of the output of the first phase locked loop at a value approximately greater than or equal to the frequency of an output of the second phase locked loop; and

programming the output of the second phase locked loop and the output of the third phase locked loops to provide different clock frequencies.

18. The method of claim 17, further comprising:

coupling the output of the second phase locked loop to at least one clocked circuit of a data channel circuit.