Body contacted dynamic memory
First Claim
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1. A dynamic memory circuit comprising:
- a storage transistor having a body contacted by a body terminal, a gate terminal connected to a fixed potential, a source contacted by a source terminal, and a drain contacted by a drain terminal;
a read-word input coupled to said source terminal of said storage transistor;
a read-bit output coupled to said drain terminal of said storage transistor;
an access transistor having an access drain terminal coupled to said body terminal of said storage transistor, an access gate terminal, and an access source terminal;
p1 a write-word input coupled to said access gate terminal having at least two different operating potentials; and
a write-bit input coupled to said access source terminal.
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Abstract
A dynamic memory circuit in which the inherent bipolar transistor effect within a floating body transistor is utilized to store an information bit. A floating body of a storage transistor stores an information bit in the form of an electric charge. The floating body is charged and discharged via an access transistor during data write operations. The inherent bipolar transistor resident within the floating body transistor increases the effective capacitance of the floating body which acts as the storage node, and thereby enhances the magnitude of the discharge current which represents the stored information bit during read operations.
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Citations
13 Claims
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1. A dynamic memory circuit comprising:
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a storage transistor having a body contacted by a body terminal, a gate terminal connected to a fixed potential, a source contacted by a source terminal, and a drain contacted by a drain terminal; a read-word input coupled to said source terminal of said storage transistor; a read-bit output coupled to said drain terminal of said storage transistor; an access transistor having an access drain terminal coupled to said body terminal of said storage transistor, an access gate terminal, and an access source terminal;
p1 a write-word input coupled to said access gate terminal having at least two different operating potentials; anda write-bit input coupled to said access source terminal. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A dynamic memory cell comprising:
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a storage silicon-on-insulator (SOI) field-effect transistor (FET) including; an N-type source terminal; an N-type drain terminal; a P-type floating body contacting the N-type source terminal and the N-type drain terminal contact, wherein the P-type floating body stores an information bit, and wherein said P-type floating body comprises the base of an inherent bipolar transistor having an emitter that corresponds to said N-type source terminal, and a collector that corresponds to said N-type drain terminal, such that the P-type floating body and N-type source terminal form a PN junction that is biased in accordance with voltage differential between said RWL and the floating body charge; a read word line (RWL) signal coupled to the N-type source terminal for accessing the information bit; and a read bit line (RBL) signal coupled from the N-type drain terminal for detecting the information bit in response said RWL signal being applied to the N-type source terminal. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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Specification