Radiation hardened six transistor random access memory and memory device

• US 6,111,780 A
• Filed: 06/04/1999
• Issued: 08/29/2000
• Est. Priority Date: 06/05/1998
• Status: Expired due to Term

• Current Assignee: Gula Consulting Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Inventors: Bertin, Robert Christian
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/325,645
• Time in Patent Office: 452 Days
• Field of Search: 365/154, 365/156, 257/371, 257/372
• US Class Current: 365/154
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A memory device can include a radiation hardened, static random access memory (SRAM) cell having a first inverter pair including a first PFET and a first NFET coupled in series drain to drain by a resistor whose resistance can be an order of magnitude (i.e., ten times) larger than the source to drain resistance of the first PFET, a second inverter pair including a second PFET and a second NFET coupled in series drain to drain by a resistor whose resistance can be an order of magnitude larger than the source to drain resistance of the second PFET, the first or second PFET can include a P+ drain difflusion in an NWELL where a portion of the gate can overlie the P+ drain diffusion, a first pass gate PFET coupled to the gate of the first PFET, the gate of the first NFET, and the P+ drain diffusion of the second PFET, and a second pass gate PFET coupled to the gate of the second PFET, the gate of the second NFET, and the P+ drain diffusion of the first PFET.

Claims

1. A radiation hardened storage cell, comprising in combination:

a first inverter pair comprised of a first PFET and a first NFET coupled in series drain to drain by a resistor whose resistance is an order of magnitude larger than the source to drain resistance of the first PFET;

said first PFET including a P+ drain diffusion in an NWELL with a portion of the gate overlying the P+ drain diffusion;

a second inverter pair comprised of a second PFET and a second NFET coupled in series drain to drain by a resistor whose resistance is an order of magnitude larger than the source to drain resistance of the second PFET;

said second PFET including a P+ drain diffusion in an NWELL with a portion of the gate overlying the P+ drain diffusion;

a first pass gate PFET coupled to the gate of said first PFET, the gate of said first NFET, and the P+ drain diffusion of said second PFET; and

a second pass gate PFET coupled to the gate of said second PFET, the gate of said second NFET, and the P+ drain diffusion of said first PFET.

2. The storage cell according to claim 1, wherein said portions of the gate overlying the P+ drain diffusion provide additional capacitance.

3. The storage cell according to claim 2, wherein the additional capacitance is between 0.2 and 0.5 pico-farads.

4. A radiation hardened storage cell, comprising:

a first inverter including a first PFET and a first NFET having commonly coupled gates and separate drains, the drain of said first PFET including a P+ drain diffusion in an NWELL with a portion of the gate overlying the P+ drain diffusion;

a second inverter including a second PFET and a second NFET having commonly coupled gates and separate drains, the drain of said second PFET including a P+ drain diffusion in an NWELL with a portion of the gate overlying the P+ drain diffusion;

first and second resistors coupling the P+ drain diffusions of the first and second PFETs respectively to the drains of the first and second NFETs;

a first pass gate PFET having a drain coupled to the commonly coupled gates of said first inverter and the P+ drain diffusion of said second PFET; and

a second pass gate PFET having a drain coupled to the commonly coupled gates of said second inverter and the P+ drain diffusion of said first PFET.

5. The storage cell according to claim 4, wherein each of said first and second PFETs have a source to drain resistance that is smaller in value than a value of a corresponding one of said resistors.

6. The storage cell according to claim 5, wherein the value of each of said resistors is an order of magnitude larger than the source to drain resistance of each of said first and second PFETs.

7. The storage cell according to claim 5, wherein the value of each of said resistors is selected to raise an immunity of the storage cell to single event upset.

8. The storage cell according to claim 4, wherein said portions of the gate overlying the P+ drain diffusion provide additional capacitance.

9. The storage cell according to claim 8, wherein the additional capacitance is selected to raise an immunity of the cell to single event upset.

10. The storage cell according to claim 8, wherein the additional capacitance is 0.2-0.5 pico-farads.

11. A memory device, comprising:

addressing circuitry;

an array of word lines and complementary bit line pairs coupled to the addressing circuitry;

a plurality of storage cells located at the intersection of selected word lines and bit line pairs;

a sense amplifier coupled to the complementary bit line pairs; and

wherein each of said plurality of storage cells comprises;

a first inverter including a first PFET and a first NFET having commonly coupled gates and separate source/drain regions, the source/drain region of said first PFET including a P+ drain diffusion in an NWELL with a portion of the gate overlying the P+ drain diffusion;

a second inverter including a second PFET and a second NFET having commonly coupled gates and separate source/drain regions, the source/drain region of said second PFET including a P+ drain diffusion in an NWELL with a portion of the gate overlying the P+ drain diffusion;

first and second resistors coupling the P+ drain diffusions of the first and second PFETs respectively to the source/drain regions of the first and second NFETs;

a first pass gate PFET having a source/drain region coupled to the commonly coupled gates of said first inverter and the P+ drain diffusion of said second PFET; and

a second pass gate PFET having a source/drain region coupled to the commonly coupled gates of said second inverter and the P+ drain diffusion of said first PFET.

12. An apparatus, comprising:

an electronic system; and

a memory device coupled to said electronic system, wherein said memory device includes a radiation hardened storage cell, having;

a first inverter including a first PFET and a first NFET having commonly coupled gates and separate source/drain regions, the source/drain region of said first PFET including a P+ drain diffusion in an NWELL with a portion of the gate overlying the P+ drain diffusion;

a second inverter including a second PFET and a second NFET having commonly coupled gates and separate source/drain regions, the source/drain region of said second PFET including a P+ drain diffusion in an NWELL with a portion of the gate overlying the P+ drain diffusion;

first and second resistors coupling the P+ drain diffusions of the first and second PFETs respectively to the source/drain regions of the first and second NFETs;

a first pass gate PFET having a source/drain region coupled to the commonly coupled gates of said first inverter and the P+ drain diffusion of said second PFET; and

a second pass gate PFET having a source/drain region coupled to the commonly coupled gates of said second inverter and the P+ drain diffusion of said first PFET.

13. The apparatus of claim 12, wherein each of said first and second PFETs have a source to drain resistance that is smaller in value than a value of a corresponding one of said resistors.

14. The apparatus of claim 13, wherein the value of each of said resistors is an order of magnitude larger than the source to drain resistance of each of said first and second PFETs.

15. The apparatus of claim 13, wherein the value of each of said resistors is selected to raise an immunity of the memory cell to single event upset.

16. The apparatus of claim 12, wherein said portions of the gate overlying the P+ drain diffusion provide additional capacitance.

17. The apparatus of claim 12, wherein the electronic system comprises a microprocessor.

18. The apparatus of claim 16, wherein the additional capacitance is selected to raise an immunity of the cell to single event upset.

19. The apparatus of claim 16, wherein the additional capacitance is 0.2-0.5 pico-farads.

20. A method of operating a radiation hardened storage cell comprising:

sustaining a SEU event particle hit on a node of the storage cell which changes the logic state at the output of an inverter of the storage cell;

recovering from a critical charge deposited on the storage cell as a result of the SEU event on the node; and

increasing RC delay slowing feedback propagation through cross-coupled inverter pair allowing more time for recovery wherein write cycle time is not appreciably affected.

21. The method of claim 20, including at least one of the following:

increasing the immunity of critical charge deposition and decreasing the voltage change on the struck node by increasing capacitance on an inverter source/drain region;

limiting the amount of voltage drop using a resistive barrier to protect against N+ transistor hits; and

generating additional charge from overlap capacitance between gate and drain regions of cross-coupled inverters wherein some of the voltage change from the particle hit can be coupled through said overlap capacitance splitting deposited charge between opposing nodes of the cross-coupled inverters.