Synchronous burst nonvolatile semiconductor memory

• US 6,111,815 A
• Filed: 10/14/1999
• Issued: 08/29/2000
• Est. Priority Date: 11/19/1998
• Status: Expired due to Fees

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Takeda, Keiichiro
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US09/418,307
• Time in Patent Office: 320 Days
• Field of Search: 365/230.08, 365/236, 365/238.5, 365/189.05, 365/189.12, 365/240
• US Class Current: 365/236
• CPC Class Codes: G11C 17/12 using field-effect devices

Abstract

A synchronous semiconductor burst nonvolatile semiconductor memory includes first and second address counter circuits and a counter selection circuit in order to output an address signal to a first latch circuit for storing therein data from a memory cell. Either the first address counter circuit or the second address counter circuit is alternately selected by the counter selection circuit in response to a burst control signal. According to the invention, either the first address counter circuit or the second address counter circuit is always selected, and a burst address signal is outputted to the latch circuit on the basis of an externally supplied address signal (first signal of the burst address signal) before the burst control signal is generated.

Claims

1. A semiconductor burst nonvolatile semiconductor memory comprising:

a memory cell group for storing data therein;

an input terminal group to which an address signal is supplied;

an intermediate terminal;

an output terminal group;

a latch circuit which stores data read out from the memory cell group and outputs the same data from an address indicated by a signal supplied to the output terminal group;

a first address counter circuit and a second address counter circuit coupled respectively between the input terminal group and the intermediate terminal group, each address counter circuit of the first address counter circuit and the second address counter circuit latching therein an address signal which is supplied to the input terminal group, and outputting the latched address signal to the intermediate terminal group and a burst address signal generated by itself to the intermediate terminal group when receiving a first burst control signal of first level and selected by selection signals, each address counter circuit of the first address counter circuit and the second address counter circuit transferring the address signal which is supplied to the input terminal group to the intermediate terminal group when receiving a first burst control signal of second level and selected by the selection signals;

a selection circuit which outputs the selection signals to alternately select either the first address counter circuit or the second address counter circuit in response to a second burst control signal; and

a decoder circuit which decodes a signal which is supplied to the intermediate terminal group and outputting the decoded signal to the output terminal group.

2. The semiconductor burst nonvolatile semiconductor memory according to claim 1, wherein the first burst control signal is the second burst control signal.

3. The semiconductor burst nonvolatile semiconductor memory according to claim 1, wherein the address signal which is supplied to the input terminal group is an externally supplied address signal.

4. A semiconductor burst nonvolatile semiconductor memory comprising:

a memory cell group for storing data therein;

an input terminal group to which an address signal is supplied;

an output terminal group;

a latch circuit which stores data read out from the memory cell group and which outputs the same data from an address indicated by a signal supplied to the output terminal group;

a first address generation circuit and a second address generation circuit coupled respectively between the input terminal group and the output terminal group, said first address generation circuit having a first address counter circuit and a first decoder circuit, said second address generation circuit having a second address counter circuit and a second decoder circuit, each address generation circuit latching therein an address signal which is supplied from the input terminal group, and decoding the latched address signal to output the decoded address signal to the output terminal group, also decoding an address signal generated by itself to output the decoded address signal to the output terminal group when receiving a first burst control signal of first level and selected by the selection signals, said each address generation circuit decoding an address signal supplied from the input terminal group and outputting the decoded address signal to the output terminal group when receiving a first burst control signal of second level and selected by the selection signals; and

a selection circuit which outputs the selection signals to alternately select either the first address generation circuit or the second address generation circuit in response to a second burst control signal.

5. The semiconductor burst nonvolatile semiconductor memory according to claim 4, wherein the first burst control signal is the second burst control signal.

6. The semiconductor burst nonvolatile semiconductor memory according to claim 4, wherein the address signal which is supplied to the input terminal group is an externally supplied address signal.

7. A semiconductor burst nonvolatile semiconductor memory comprising:

a memory cell group for storing data therein;

an input terminal group to which an address signal is supplied;

an output terminal group;

a latch circuit which stores data read out from the memory cell group and outputs the same data from an address indicated by a signal supplied to the output terminal group;

a decoder circuit for decoding an address signal supplied to the input terminal group;

a first shift register and a second shifter register, each shift register being coupled to an output of the decoder circuit and the output terminal group, said each shift register latching therein an output signal of the decoder circuit and outputting the latched output signal to the output terminal group and outputting an address signal generated by itself to the output terminal group when receiving a first burst control signal of first level and selected by selection signals, said each shift register transferring the output signal outputted by the decoder circuit to the output terminal group when receiving a first burst control signal of second level and selected by the selection signal; and

a selection circuit which outputs the selection signals to alternately select either the first shift register or the second shift register in response to a second burst control signal.

8. The semiconductor burst nonvolatile semiconductor memory according to claim 7, wherein the first burst control signal is the second burst control signal.

9. The semiconductor burst nonvolatile semiconductor memory according to claim 7, wherein the address signal which is supplied to the input terminal group is an externally supplied address signal.