Data transfer network on a computer chip utilizing combined bus and ring topologies

• US 6,111,859 A
• Filed: 10/24/1997
• Issued: 08/29/2000
• Est. Priority Date: 01/16/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hartmann, Alfred C., Godfrey, Gary M., Lambrecht, J. Andrew
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): SLAVITT, MITCHELL R
• Application Number:
  US08/957,589
• Time in Patent Office: 1,040 Days
• Field of Search: 370/257, 370/258, 370/364, 370/424, 370/489, 709/251, 709/252, 709/253, 710/100
• US Class Current: 370/257
• CPC Class Codes: H04L 12/42 Loop networks
• CPC Class Codes: H04L 69/08 Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A computer chip includes a data transfer network. The data transfer network comprises a backbone bus, a plurality of communication ports and a plurality of devices or modules each coupled to the backbone bus. Each of the devices includes or is coupled to one or more communication ports. Some of communication ports are operable to transmit and receive data on the backbone bus. Furthermore, the communication ports are interconnected in a ring topology forming a circular bus or a semi-circular bus. A subset of the communication ports may transmit and receive data on the circular bus or semi-circular bus. For the semi-circular bus, the communication ports are not coupled to form a complete ring topology. The communication ports may be operable to communicate with each other over the backbone bus and/or the circular bus. Each of the communication ports includes backbone bus interface logic, circular bus interface logic, one or more data transfer buffers and/or control logic. The communication ports are preferably able to transfer communications between the backbone bus, the circular bus and/or the modules.

Claims

1. A computer chip comprising a data transfer network, the data transfer network comprising:

a backbone bus;

a plurality of communication ports coupled to the backbone bus, wherein at least a subset of the plurality of communication ports are operable to transmit and receive data on the backbone bus;

wherein the plurality of communication ports are further interconnected in a ring topology forming a circular bus, wherein at least a subset of the plurality of communication ports are operable to transmit and receive data on the circular bus;

wherein said plurality of communication ports comprises a first plurality of communication ports coupled to a first side of said backbone bus, and a second plurality of communication ports coupled to a second side of said backbone bus;

wherein said first plurality of communication ports are directly electrically coupled forming a first portion of said circular bus, and wherein said second plurality of communication ports are directly electrically coupled forming a second portion of said circular bus;

wherein said first plurality of communication ports includes a first communication port and a last communication port, and wherein said second plurality of communication ports includes a first communication port and a last communication port;

wherein said first communication port of said first plurality of communication ports is coupled to said first communication port of said second plurality of communication ports, and wherein said last communication port of said first plurality of communication ports is coupled to said last communication port of said second plurality of communication ports, thereby forming a circular bus between said communication ports;

a plurality of modules, wherein each of said plurality of modules is coupled to at least one of said plurality of communication ports, wherein said plurality of modules are operable to communicate with each other through said communication ports.

2. The computer chip of claim 1, wherein one or more of said first plurality of communication ports coupled to said first side of said backbone bus are operable to communicate over said backbone bus to one or more of said second plurality of communication ports coupled to said second side of said backbone bus;

wherein one or more of said first plurality of communication ports coupled to said first side of said backbone bus are operable to communicate over said circular bus to one or more of said second plurality of communication ports coupled to said second side of said backbone bus.

3. The computer chip of claim 2, wherein each of said first plurality of communication ports and said second plurality of communication ports are operable to selectively communicate over either said backbone bus or said circular bus.

4. The computer chip of claim 1, wherein said data transfer network is operable in a first mode wherein each of said first plurality of communication ports and said second plurality of communication ports communicate only using said backbone bus, and wherein said data transfer network is operable in a second mode wherein each of said first plurality of communication ports and said second plurality of communication ports communicate only using said circular bus.

5. The computer chip of claim 1, wherein each of said communication ports comprises:

backbone bus interface logic coupled to said backbone bus;

circular bus interface logic coupled to said circular bus;

one or more data transfer buffers, wherein at least a first portion of said one or more data transfer buffers is coupled to said circular bus interface logic, wherein said first portion of said one or more data transfer buffers is configurable to communicate information between said module and said circular bus;

wherein at least a second portion of said one or more data transfer buffers is coupled to said backbone bus interface logic, wherein said second portion of said one or more data transfer buffers is configurable to communicate information between said module and said backbone bus, wherein one or more of said first portion and said second portion of said one or more data transfer buffers is configurable to communicate information between said backbone bus and said circular bus.

6. The computer chip of claim 1, further comprising:

a plurality of buffers, wherein each of the plurality of buffers is coupled between a respective communication port and the backbone bus;

wherein the plurality of buffers are operable for buffering data between a respective communication port and the backbone bus.

7. The computer chip of claim 1, further comprising:

a plurality of buffers, wherein each of the plurality of buffers is coupled between a respective communication port and the circular bus;

wherein the plurality of buffers are operable for buffering data between a respective communication port and the circular bus.

8. The computer chip of claim 1, wherein each of said modules performs one or more operations, wherein said operations comprise a processor, a memory, an I/O controller, a task-specific hybrid, and a task-general hybrid.

9. The computer chip of claim 1, wherein one or more of said backbone bus and said circular data bus include addressing and control lines.

10. The computer chip of claim 1, wherein the circular bus is configured in a multiple ring topology.

11. A computer chip comprising a data transfer network, the computer chip comprising:

a backbone bus;

a plurality of communication ports coupled to the backbone bus, wherein at least a subset of the plurality of communication ports are operable to transmit and receive data on the backbone bus;

wherein the plurality of communication ports are further interconnected in a half-ring topology forming a semi-circular bus, wherein at least a subset of the plurality of communication ports are operable to transmit and receive data on the semi-circular bus;

wherein said plurality of communication ports comprises a first plurality of communication ports coupled to a first side of said backbone bus, and a second plurality of communication ports coupled to a second side of said backbone bus;

wherein said first plurality of communication ports are electrically coupled forming a first portion of said circular bus, and wherein said second plurality of communication ports are directly electrically coupled forming a second portion of said circular bus;

wherein said first plurality of communication ports includes a first communication port and a last communication port, and wherein said second plurality of communication ports includes a first communication port and a last communication port;

wherein said first communication port of said first plurality of communication ports is coupled to said first communication port of said second plurality of communication ports, thereby forming a semi-circular bus between said communication ports;

a plurality of modules, wherein each of said plurality of modules is coupled to at least one of said plurality of communication ports, wherein said plurality of modules are operable to communicate with each other through said communication ports.

12. The computer chip of claim 11, wherein said last communication port of said first plurality of communication ports is not coupled to said last communication port of said second plurality of communication ports.

13. A computer chip comprising a data transfer network, the computer chip comprising:

a backbone bus;

a plurality of devices coupled to the backbone bus, wherein each of said devices includes one or more communication ports coupled to the backbone bus, wherein at least a subset of the plurality of communication ports are operable to transmit and receive data on the backbone bus;

wherein the plurality of communication ports are further interconnected in a ring topology forming a circular bus, wherein at least a subset of the plurality of communication ports are operable to transmit and receive data on the circular bus;

wherein said plurality of communication ports comprises a first plurality of communication ports coupled to a first side of said backbone bus, and a second plurality of communication ports coupled to a second side of said backbone bus;

wherein said first plurality of communication ports are directly electrically coupled forming a first portion of said circular bus, and wherein said second plurality of communication ports are directly electrically coupled forming a second portion of said circular bus;

wherein said first plurality of communication ports includes a first communication port and a last communication port, and wherein said second plurality of communication ports includes a first communication port and a last communication port;

wherein said first communication port of said first plurality of communication ports is coupled to said first communication port of said second plurality of communication ports, and wherein said last communication port of said first plurality of communication ports is coupled to said last communication port of said second plurality of communication ports, thereby forming a circular bus between said communication ports;

wherein said plurality of devices are operable to communicate with each other through said communication ports.

14. The computer chip of claim 13, further comprising:

a plurality of buffers, wherein each of the first plurality of buffers is coupled between a respective communication port, the backbone bus and the circular bus;

wherein each of the plurality of buffers is operable for buffering data between a respective communication port and either the backbone bus or the circular bus,

wherein each of the plurality of buffers is operable for buffering data between the backbone bus and the circular bus.

15. The computer chip of claim 13, wherein the circular bus is configured in a multiple ring topology.

16. A computer chip comprising a data transfer network, the data transfer network comprising:

a backbone bus;

a plurality of communication ports coupled to the backbone bus, wherein at least a subset of the plurality of communication ports are operable to transmit and receive data on the backbone bus;

wherein the plurality of communication ports are further interconnected in a ring topology forming a circular bus, wherein at least a subset of the plurality of communication ports are operable to transmit and receive data on the circular bus;

a plurality of modules, wherein each of said plurality of modules is coupled to at least one of said plurality of communication ports, wherein said plurality of modules are operable to communicate with each other through said communication ports;

wherein said data transfer network is operable in a first mode wherein each of a first plurality of communication ports and a second plurality of communication ports communicate only using said backbone bus, and wherein said data transfer network is operable in a second mode wherein each of said first plurality of communication ports and said second plurality of communication ports communicate only using said circular bus.

17. A computer chip comprising a data transfer network, the data transfer network comprising:

a backbone bus;

a plurality of communication ports coupled to the backbone bus, wherein at least a subset of the plurality of communication ports are operable to transmit and receive data on the backbone bus;

wherein the plurality of communication ports are further interconnected in a ring topology forming a circular bus, wherein at least a subset of the plurality of communication ports are operable to transmit and receive data on the circular bus;

a plurality of modules, wherein each of said plurality of modules is coupled to at least one of said plurality of communication ports, wherein said plurality of modules are operable to communicate with each other through said communication ports;

wherein each of said communication ports comprises;

backbone bus interface logic coupled to said backbone bus;

circular bus interface logic coupled to said circular bus;

one or more data transfer buffers, wherein at least a first portion of said one or more data transfer buffers is coupled to said circular bus interface logic, wherein said first portion of said one or more data transfer buffers is configurable to communicate information between said module and said circular bus;

wherein at least a second portion of said one or more data transfer buffers is coupled to said backbone bus interface logic, wherein said second portion of said one or more data transfer buffers is configurable to communicate information between said module and said backbone bus, wherein one or more of said first portion and said second portion of said one or more data transfer buffers is configurable to communicate information between said backbone bus and said circular bus.

18. A computer chip comprising a data transfer network, the data transfer network comprising:

a backbone bus;

a plurality of communication ports coupled to the backbone bus, wherein at least a subset of the plurality of communication ports are operable to transmit and receive data on the backbone bus;

wherein the plurality of communication ports are further interconnected in a ring topology forming a circular bus, wherein at least a subset of the plurality of communication ports are operable to transmit and receive data on the circular bus;

a plurality of modules, wherein each of said plurality of modules is coupled to at least one of said plurality of communication ports, wherein said plurality of modules are operable to communicate with each other through said communication ports;

a plurality of buffers, wherein each of the plurality of buffers is coupled between a respective communication port and the backbone bus;

wherein the plurality of buffers are operable for buffering data between a respective communication port and the backbone bus.

19. A computer chip comprising a data transfer network, the data transfer network comprising:

a backbone bus;

a plurality of communication ports coupled to the backbone bus, wherein at least a subset of the plurality of communication ports are operable to transmit and receive data on the backbone bus;

wherein the plurality of communication ports are further interconnected in a ring topology forming a circular bus, wherein at least a subset of the plurality of communication ports are operable to transmit and receive data on the circular bus;

a plurality of modules, wherein each of said plurality of modules is coupled to at least one of said plurality of communication ports, wherein said plurality of modules are operable to communicate with each other through said communication ports;

a plurality of buffers, wherein each of the plurality of buffers is coupled between a respective communication port and the circular bus;

wherein the plurality of buffers are operable for buffering data between a respective communication port and the circular bus.