Direct sequence frequency ambiguity resolving receiver

• US 6,111,911 A
• Filed: 06/07/1995
• Issued: 08/29/2000
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: Globalstar Incorporated, M&FC Holding, LLC
• Original Assignee: Sanconix Inc.
• Inventors: Rouquette, Robert E., Sanderford, H. Britton Jr., Davis, Robert J.
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US08/485,007
• Time in Patent Office: 1,910 Days
• Field of Search: 375/347, 375/349, 375/350, 375/367, 375/130, 375/140, 375/141, 375/143, 375/147, 375/152, 370/342, 370/441, 370/479, 370/335, 370/320
• US Class Current: 375/147
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/70752 Partial correlation
• CPC Class Codes: H04B 1/70755 Setting of lock conditions, e.g. threshold
• CPC Class Codes: H04B 1/70775 Multi-dwell schemes, i.e. multiple accumulation times
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/7097 Interference-related aspects
• CPC Class Codes: H04B 1/7101 with estimation filters

Abstract

A system and method for receiving direct sequence spread spectrum transmissions with both chip code and frequency uncertainty including a parallel frequency acquisition technique for increasing receiver sensitivity and increasing process gain while reducing a preamble duration required for spread spectrum acquisition. The system and method include techniques for reducing effects of jamming and impulse noise on receiver performance via enhanced antenna diversity by constructively combining received signals. Further, techniques are provided which compensate for chip code alignment drift, providing an associated transmitter maintains carrier and chip code coherence, by comparing received signal energies at varying chip code alignments. These techniques enable the use of lower cost frequency setting crystals in both the receiver and transmitter as well as provide for system operation over a wider temperature range.

Claims

1. A direct sequence spread spectrum system, comprising:

a transmitter configured to transmit a direct sequence spread spectrum signal that includes a carrier frequency modulated by a direct sequence chip code, a phase synchronizing preamble, and modulating information; and

a receiver configured to receive the transmitted direct sequence spread spectrum signal with both chip code phase uncertainty and frequency uncertainty between the carrier frequency of the transmitter and a local reference frequency of the receiver and to demodulate the modulating information, comprising,

a despreader which despreads the received direct sequence spread spectrum signal to produce a despread signal,

a plurality of parallel filters having adjacent bandpass ranges, each parallel filter having the despread signal applied thereto and each parallel filter having a bandwidth less than said frequency uncertainty,

an operator mechanism configured to detect outputs of said parallel filters and to select a parallel filter based on the detected parallel filter outputs to resolve said carrier frequency uncertainty, and

a demodulator configured to demodulate data having a data bandwidth at the output of the selected filter.

2. The system according to claim 1, wherein the bandwidth of each of said plural parallel filters is matched to a bandwidth of the modulated information.

3. The system according to claim 1, wherein each of the plurality of parallel filters has a bandwidth less than the data bandwidth during demodulation.

4. The system according to claim 1, wherein each of the plurality of parallel filters has a bandwidth less than or equal to approximately one half of the carrier frequency uncertainty.

5. The system according to claim 1, wherein each of the plurality of parallel filters has a bandwidth in a range of approximately one tenth to one half of the carrier frequency uncertainty.

6. The system according to claim 1, wherein the despreader comprises:

a code reference generator configured to provide a chip code, and

a mixer for mixing said chip code and a frequency converted direct sequence spread spectrum signal received at an output of a frequency conversion stage to produce the despread signal provided to the plurality of filters.

7. The system according to claim 1, wherein said demodulator demodulates at least one of voice and data from the output of the selected filter.

8. The system according to claim 1, wherein said operator mechanism selects one of said plurality of parallel filters having a strongest signal level above a predetermined minimum level.

9. The system according to claim 1, wherein said operator mechanism detects at an output of each of the plurality of parallel filters at least one of a) signal strength, b) quieting, c) phase lock, and d) signal quality.

10. The system according to claim 1, wherein the operator mechanism comprises a calculator configured to calculate an average signal strength of outputs of said plurality of parallel filters with at least one of a highest and a lowest signal strength eliminated from calculation of the average, and selects a filter having an output signal strength exceeding the calculated average by a predetermined margin.

11. The system according to claim 1, wherein said operator mechanism selects a filter based on outputs of parallel filters having stronger signal levels by a predetermined margin than outputs of others of said parallel filters.

12. The system according to claim 1, wherein the plurality of parallel filters comprise a Fourier transform mechanism configured to detect signal strengths of discrete frequency ranges based on a data bandwidth and covering a total bandwidth at least as large as said frequency uncertainty.

13. The system according to claim 1, wherein the receiver further comprises a plurality of envelope shaping devices coupled between the despreader and the plurality of filters and configured to reduce impulse effects on signals passed by filters adjacent to the selected filter.

14. The system according to claim 1, wherein the despreader comprises a parallel correlator.

15. The system according to claim 14, wherein the parallel correlator includes a clock input which receives a parallel correlator clock clocked at a chipping rate.

16. The system according to claim 14, wherein said parallel correlator comprises a correction mechanism configured to correct a parallel correlator clock in time by a portion of a chip duration.

17. The system according to claim 1, wherein the receiver further comprises:

a frequency reference device that provides a frequency reference for mixing with incoming signals;

a temperature measurement device for providing a temperature of said receiver;

a frequency reference correction device for calculating a frequency correction factor based on said temperature; and

a drift correction device for providing a frequency drift correction factor to said frequency reference device based on said temperature.

18. The system according to claim 1, wherein the receiver further comprises:

a jamming warning mechanism configured to provide a jamming warning when a majority of the plurality of filter outputs simultaneously exceeds a predetermined signal strength.

19. The system according to claim 1, wherein said operator mechanism is configured to interpolate a frequency between outputs of adjacent ones of said filters having predetermined signal strengths based on a ratio of received signal energies between the adjacent filter outputs and selects the output of a filter centered at the interpolated frequency.

20. In a direct sequence spread spectrum system for receiving a direct sequence spread spectrum signal with both chip code phase uncertainty and frequency uncertainty between a carrier frequency of a transmitter transmitting said direct sequence spread spectrum signal and a local reference frequency utilized by a receiver, the receiver comprising:

a despreader configured to despread a received direct sequence spread spectrum signal, comprising,

a memory configured to store tables of coefficients, each said table of said coefficients being a product of a respective chip code sequence and at least one respective bandpass filter characteristic and a lowpass filter characteristic, each bandpass filter characteristic being one of a plurality of adjacent frequency filter characteristics,

a multiplier configured to multiply in parallel the received direct sequence spread spectrum signal and the coefficients of a plurality of said coefficient tables thereby to implement plural parallel filters producing plural parallel despread output signals each corresponding to a filter output corresponding to a respective one of said tables of coefficients;

an operator mechanism configured to detect at said filter outputs at least one parameter selected from the group consisting of a) signal strength, b) quieting, c) phase lock, and d) signal quality and based on the at least one detected parameter to select an output of a filter for demodulation; and

a demodulator configured to demodulate data having a data bandwidth at the selected filter output.

21. The system according to claim 20, wherein the bandwidth of each of said plural filters is matched to the data bandwidth of data modulated on said received direct sequence spread spectrum signal.

22. The system according to claim 21, wherein each of the plural parallel filters has a bandwidth less than the data bandwidth during demodulation.

23. The system according to claim 20, wherein each of the plurality of filters has a bandwidth less than a reciprocal of a repetition rate of a code sequence of the despreader.

24. The system according to claim 20, wherein each of the plurality of filters has a bandwidth less than or equal to approximately one half of the carrier frequency uncertainty.

25. The system according to claim 20, wherein each of the plurality of filters has a bandwidth in a range of approximately one tenth to one half of the carrier frequency uncertainty.

26. The system according to claim 20, wherein said operator mechanism selects one of said plurality of filters having a strongest signal level above a predetermined minimum level.

27. The system according to claim 20, wherein the operator mechanism comprises a calculator configured to calculate an average signal strength of said filter outputs with at least one of a highest and a lowest signal strength eliminated from calculation of the average, and selects a filter having an output exceeding the calculated average by a predetermined margin.

28. The system according to claim 20, wherein said operator mechanism selects a filter based on outputs of adjacent filters having stronger signal levels than outputs of others of said filters.

29. The system according to claim 20, wherein the despreader comprises a parallel correlator.

30. The system according to claim 29, wherein the parallel correlator includes a clock input which receives a parallel correlator clock clocked at a chipping rate.

31. The system according to claim 29, wherein said parallel correlator comprises a correction mechanism configured to correct a parallel correlator clock in time by a portion of a chip duration.

32. The system according to claim 20, wherein each of the plurality of parallel filters has a bandwidth less than the data bandwidth during demodulation.

33. The system according to claim 20, wherein

said despreader further comprises a local reference frequency device that provides said local reference frequency for mixing with said received direct sequence spread spectrum signal;

and

said system further comprises;

a temperature measurement device for providing a temperature of said system;

a frequency reference correction device for calculating a frequency correction factor based on said temperature; and

a drift correction device for providing a frequency drift correction factor to said local reference frequency device based on said temperature.

34. The system according to claim 20, further comprising:

a jamming warning mechanism configured to provide a jamming warning when a majority of the plurality of filter outputs simultaneously exceeds a predetermined signal strength.

35. The system according to claim 20, wherein said operator mechanism is configured to interpolate a frequency between outputs of adjacent ones of said filters having predetermined signal strengths based on a ratio of received signal energies between the adjacent filter outputs and selects the output of a filter centered at the interpolated frequency.

36. In a direct sequence spread spectrum receiver, a method for receiving a transmitted direct sequence spread spectrum signal, comprising the steps of:

despreading a received direct sequence spread spectrum signal by mixing the received signal with a chip code reference signal;

applying the despread signal simultaneously to a plurality of parallel filters, each filter of said plurality of filters having a bandwidth based on a reference chip code rate and chip code length of said receiver, where said bandwidth is less than a frequency uncertainty between the transmitted and received direct sequence spread spectrum signals;

detecting at an output of each of the plurality of filters at least one parameter of a) signal strength, b) quieting, c) phase lock, and d) signal quality;

selecting for data demodulation an output of a filter based upon the at least one parameter detected at the output of each of said plurality of filters; and

demodulating one of data having a data bandwidth and voice information from the selected filter output.

37. The method according to claim 36, further comprising the step of pipelining an output of each filter in said plurality of filters to sample storage buffers.

38. The method according to claim 36, further comprising the steps of:

detecting a signal strength at each filter output of the plurality of filters;

comparing the detected signal strength at each filter output to a predetermined signal strength; and

providing a jamming warning when a majority of the signal strengths of the plurality of filter outputs simultaneously exceed said predetermined signal strength.

39. The method according to claim 36, further comprising the steps of:

counteracting signal fading comprising;

measuring, during reception of a transmitted preamble, a first phase of a first signal from a first antenna,

measuring, during the reception of the transmitted preamble, a second phase of a second signal from a second antenna,

computing, as a phase correction factor, a difference between the first and second phases,

applying the phase correction factor to a phase delaying device which constructively combines the first and second signals from the first and second antennas in phase with each other; and

demodulating data from the constructively combined first and second signals.

40. The method according to claim 36, further comprising:

measuring, during reception of a transmitted preamble, a first signal strength of a first antenna, and a second signal strength of a second antenna;

comparing the first and second signal strengths;

determining, upon comparison of the first and second signal strengths, a stronger signal strength antenna;

enabling, based upon the determining step, only the stronger signal strength antenna; and

demodulating data, upon completion of the transmitted preamble, with only the stronger signal strength antenna enabled.

41. The method according to claim 36, further comprising:

establishing the bandwidth of each of the plural parallel filters at less than the data bandwidth prior to demodulation; and

establishing the bandwidth of the filter having the selected output to be at least equal to the data bandwidth during demodulation.

42. The method according to claim 36, wherein the step of selecting for data demodulation comprises:

interpolating a frequency between outputs of adjacent ones of said parallel filters having predetermined signal strengths based on a ratio of received signal energies between the adjacent filter outputs; and

selecting the output of a filter centered at the interpolated frequency.

43. A receiving method employed in a direct sequence spread spectrum receiver for receiving a direct sequence spread spectrum signal with time uncertainty in a chip code alignment and frequency uncertainty between a carrier frequency of a transmitter and a local reference frequency of the receiver, the method comprising the steps of:

despreading a received direct sequence spread spectrum signal to produce a despread signal;

applying the despread signal simultaneously to a plurality of filters each having a bandwidth based on a reference chip code rate and chip code length of said receiver, where said bandwidth is less than said frequency uncertainty;

applying a trip level algorithm to outputs of the plurality of filters, in order to achieve initial spread spectrum synchronization and resolve the time uncertainty of the chip code alignment;

selecting the output of at least one filter for subsequent demodulation based on the applying said trip level algorithm; and

demodulating the selected filter output of at least one of data having a data bandwidth and voice.

44. The method of claim 43, wherein said step of applying the trip level algorithm comprises:

determining at least one of (1) which filter output has a signal strength higher than signal strengths of other filter outputs by at least a predetermined margin, (2) which filter output has the greatest signal strength, and (3) which filter output has a signal strength higher by at least a preset margin than an average of the signal strengths of the filter outputs, wherein, in computing the average of the signal strengths, at least one of the following steps is performed;

(a) the lowest signal strength is removed from the average, (b) the highest signal strength is removed from the average, and (c) all signal strengths are used in the average.

45. The receiving method according to claim 43, further comprising:

detecting a signal strength of each filter output;

comparing the detected signal strength of each filter output to a predetermined signal strength; and

providing a jamming warning when a majority of said filter outputs simultaneously have a signal strength above said predetermined signal strength.

46. The receiving method according to claim 43, further comprising:

correcting phase drift of a chip code clock based on an offset between the center frequency of the selected filter output and the center frequency of a predetermined filter output representing zero frequency error in the absence of frequency uncertainty.

47. The method according to claim 43, wherein the selecting step comprises choosing a filter output having a largest signal strength.

48. The method according to claim 43, wherein the step of applying the trip level algorithm further comprises:

combining signal strengths of all filter outputs to obtain a combined signal strength; and

comparing the combined signal strength to a previous combined signal strength at a previous chip code alignment.

49. The method according to claim 43, further comprising:

setting adjacent channel filter attenuation such that a signal having a center frequency in one filter bandwidth is attenuated in an adjacent filter bandwidth by at least a maximum trip level.

50. The receiving method according to claim 43, wherein the step of applying the trip level algorithm comprises:

measuring and combining signal strengths at outputs of the filters, including,

determining a first combined signal strength level output by said filters at a first chip code phase alignment;

determining a second combined signal strength level output by said filters at a second chip code phase alignment; and

verifying that said second combined signal strength level exceeds the first combined signal strength level by at least a predetermined amount.

51. The method according to claim 43, further comprising:

compensating for chip code phase alignment drift of the receiver with respect to the transmitter, comprising,

measuring a frequency offset of the selected filter output with respect to the center frequency of a predetermined filter output representing zero frequency error in the absence of frequency uncertainty,

calculating a chip code phase drift correction factor based on the frequency offset;

applying the calculated chip code phase drift correction factor to produce a phase corrected chip code sequence; and

demodulating data utilizing the phase corrected chip code sequence.

52. The method according to claim 43, further comprising:

establishing the bandwidth of each of the plurality of filters at less than the data bandwidth prior to demodulation;

establishing the bandwidth of the filter having the selected output to be at least equal to the data bandwidth during demodulation.

53. The method according to claim 43, wherein:

the step of applying the trip level algorithm comprises,

interpolating a frequency between outputs of adjacent ones of said filters having predetermined signal strengths based on a ratio of received signal energies between the adjacent filter outputs; and

the step of selecting comprises,

selecting the output of a filter centered at the frequency interpolated in said trip level algorithm applying step.

54. The method according to claim 43, further comprising the step of:

jogging the chip code reference to correct for chip code phase drift.

55. The method according to claim 43, further comprising:

counteracting signal fading comprising,

measuring, during reception of a transmitted preamble, a first phase of a first signal from a first antenna,

measuring, during the reception of the transmitted preamble, a second phase of a second signal from a second antenna,

computing, as a phase correction factor, a difference between the first and second phases, and

applying the phase correction factor to a phase delaying device which constructively combines the first and second signals from the first and second antennas in phase with each other; and

demodulating data from the constructively combined first and second signals.

56. In a receiving method employed in a direct sequence spread spectrum receiver for receiving a direct sequence spread spectrum signal with time uncertainty in a chip code alignment and frequency uncertainty between a carrier frequency of a transmitter transmitting said direct sequence spread spectrum signal and a local reference frequency of the direct sequence spread spectrum receiver, the improvement comprising the steps of:

applying a trip level algorithm to the outputs of a plurality of filters in order to achieve initial spread spectrum synchronization, including,

determining at each chip code phase alignment a previous history average of outputs of said filters from at least the previous chip code phase alignment,

comparing, for each successive chip code phase alignment, the signal strength of the outputs of each of the plurality of filters to said previous history,

determining at least one filter output that is higher than said previous history, by at least a predetermined level;

selecting for demodulation an output of one of said filters which has a signal strength higher than said previous history, by at least said predetermined level based on the determined at least one filter; and

demodulating data having a data bandwidth at the output of the selected filter.

57. The method according to claim 56, further comprising:

establishing the bandwidth of each of the plurality of filters at less than the data bandwidth prior to demodulation; and

establishing the bandwidth of the filter having the selected output to be at least equal to the data bandwidth during demodulation.

58. The method according to claim 57, wherein the step of selecting for demodulation the output of one of said filters comprises:

interpolating a frequency between outputs of adjacent ones of said plurality of filters having predetermined signal strengths based on a ratio of received signal energies between the adjacent filter outputs; and

selecting the output of a filter centered at the interpolated frequency.

59. A method for receiving a direct sequence spread spectrum signal with time uncertainty in a chip code alignment and frequency uncertainty between a carrier frequency of a transmitter transmitting said direct sequence spread spectrum signal and a local reference frequency of a receiver, comprising the steps of:

despreading a received direct sequence spread spectrum signal to produce a despread signal;

applying the despread signal simultaneously to a plurality of filters each having a bandwidth based on a reference chip code rate and chip code length of said receiver, where said bandwidth is less than said frequency uncertainty; and

applying a trip level algorithm to outputs of the plurality of filters, comprising,

computing, at a first chip code alignment, a signal strength of an output of each of the filters relative to an output of a filter having a lowest signal strength,

summing the signal strengths, computed at the first chip code alignment, of all filter outputs into a first combined signal strength, computing at a second chip code alignment a signal strength of an output of each of the filters relative to an output of a filter having a lowest signal strength,

summing the signal strengths computed at the second chip code alignment, of all filter outputs into a second combined signal strength, and

comparing the second combined signal strength to the first combined signal strength to determine if the second combined signal strength exceeds the first combined signal strength by a trip level.

60. A method of receiving a direct sequence spread spectrum signal having both chip code phase uncertainty and frequency uncertainty, comprising:

despreading a received direct sequence spread spectrum signal by means of a chip code sequence to produce a despread signal;

applying the despread signal to plural filters;

selecting an output of a candidate filter from said plural filters for demodulation;

measuring a frequency offset from the candidate filter to a filter representing a zero offset frequency error in the absence of frequency uncertainty;

calculating a chip code sequence phase correction factor for compensation of code drift; and

using the chip code sequence phase correction factor to correct a phase in the chip code sequence.

61. The method according to claim 60, further comprising:

demodulating the output of said candidate filter.

62. A method of receiving a direct sequence spread spectrum signal having both chip code phase uncertainty and frequency uncertainty, comprising:

despreading the received direct sequence spread spectrum signal to produce a despread signal;

applying the despread signal to a filter bank comprising plural filters;

measuring signal strengths at outputs of each of the plural filters;

applying a trip level algorithm to determine if the measured signal strengths exceeds a predetermined value;

selecting an output of a candidate filter from said plural filters for demodulation;

measuring a frequency offset from the candidate filter output to a center frequency filter output; and

selecting, based on the frequency offset measured in said measuring step, an alternative filter bank having plural filters and a center frequency offset by a portion of a filter bandwidth.

63. A direct sequence spread spectrum system including a transmitter which transmits a spread spectrum signal comprising a direct sequence chip code and a carrier frequency, and a receiver which receives the transmitted signal and resolves carrier frequency uncertainty between the carrier frequency of the transmitter and a local reference frequency of the receiver and chip code phase uncertainty between the chip code of the transmitter and a chip code of the receiver, the system comprising:

a despreader configured to despread the received signals, comprising a chip code sequence phase shifter which shifts a phase of the receiver chip code sequence while searching to resolve said chip code phase uncertainty;

a plurality of filters each having an output of the despreader applied thereto and each having a bandwidth less than said carrier frequency uncertainty; and

an operator mechanism configured to detect outputs of said filters at consecutive code chips and to use concurrently detected outputs of the plurality of said filters to determine existence of chip code synchronization at each code chip, and to cause said chip code phase shifter to cease shifting the phase of the receiver chip code when chip code synchronization is determined to exist.

64. The system according to claim 63, wherein the operator mechanism is configured to determine existence of chip code synchronization at each code chip in relation to a minimum trip level threshold.

65. The system according to claim 63, wherein the plurality of filters comprise parallel filters.

66. The system according to claim 63, wherein the plurality of filters comprise parallel filters having adjacent pass bands.