Pipeline processing machine having a plurality of reconfigurable processing stages interconnected by a two-wire interface bus

• US 6,112,017 A
• Filed: 11/11/1997
• Issued: 08/29/2000
• Est. Priority Date: 06/30/1992
• Status: Expired due to Term

• Current Assignee: Coases Investments Bros LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Wise, Adrian Philip
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): Davis, Jr., Walter D.
• Application Number:
  US08/967,515
• Time in Patent Office: 1,022 Days
• Field of Search: 395/800.01, 395/376, 395/561, 395/308, 348/384, 348/441, 341/50, 341/126, 341/173
• US Class Current: 712/200
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Claims

1. In a pipeline processing machine having a plurality of reconfigurable processing stages interconnected by a two-wire interface bus, the improvement comprising:

one of said processing stages being a spatial decoder;

a second of said stages being a token generator for generating control tokens and data tokens for passage along said two-wire interface;

a token decode means positioned in said spatial decoder for recognizing certain of said tokens as control tokens pertinent to said spatial decoder and for configuring said spatial decoder for spatially decoding said data tokens following said control token into a first decoded format; and

a further one of said stages being a temporal decoder positioned downstream in said pipeline from said spatial decoder;

a second token decode means positioned in said temporal decoder for recognizing certain of said tokens as control tokens pertinent to said temporal decoder and for configuring said temporal decoder for temporally decoding said data tokens following said control token into a second decoded format.

3. A machine as recited in claims 1 or 2, wherein said first decoded format is a still picture format.

4. A machine as recited in claims 1 or 2, wherein said first decoded format is a moving picture format.

2. In a pipeline processing machine having a plurality of reconfigurable processing stages interconnected by a two-wire interface bus, the improvement comprising:

one of said processing stages being a spatial decoder;

a second of said stages being a token generator for generating control tokens and data tokens for passage along said two-wire interface;

a token decode means positioned in said spatial decoder for recognizing certain of said tokens as control tokens pertinent to said spatial decoder and for configuring said spatial decoder for spatially decoding said data tokens following said control token into a first decoded format; and

the temporal decoder utilizing a reconfigurable prediction filter which is reconfigurable by a prediction token.

5. In a pipeline processing machine for handling a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream and employing a plurality of stages interconnected by a two-wire interface, the improvement comprising:

a start code detector responsive to the single serial bit stream for generating control tokens and DATA tokens for application to said two-wire interface;

a token decode means positioned in certain of said stages for recognizing certain of said tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along said pipeline;

a reconfigurable temporal decoder responsive to a recognized control token for reconfiguring said temporal decoder stage to handle an identified DATA token, data being moved along said two-wire interface within said temporal decoder in 8×

8 pel data blocks; and

address means for storing and retrieving said blocks along block boundaries.

6. A machine as in claim 5, wherein said address means store and retrieve blocks of data across block boundaries.

7. A machine as in claim 5, wherein said address means reorders said blocks as picture data for display.

8. A machine as recited in any one of claims 5-7, and further comprising:

circuit means for either displaying the output of said temporal decoder or writing said output back into a picture memory location.

9. A machine as recited in either claims 5 or 6, wherein said data blocks stored and retrieved are greater and/or smaller than 8×

8 pel data blocks.