Digital filter with efficient quantization circuitry

• US 6,112,218 A
• Filed: 03/30/1998
• Issued: 08/29/2000
• Est. Priority Date: 03/30/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Gandhi, Prashant, Hochschild, James R.
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/050,391
• Time in Patent Office: 883 Days
• Field of Search: 708/320, 708/300, 708/306, 708/603
• US Class Current: 708/320
• CPC Class Codes: H03H 17/04 Recursive filters
• CPC Class Codes: H03H 17/0461 Quantisation; Rounding; Truncation; Overflow oscillations or limit cycles eliminating measures

Abstract

An infinite impulse response (IIR) digital filter and method of performing the same is disclosed. The digital filter may be realized by way of a programmable logic device, such as a digital signal processor (75), or alternatively by way of dedicated logic including adders (44, 48, 50, 54, 58, 62, 66, 70, 72) and shifters (46, 52, 56, 60, 64). In either case, addition operations (34) are interleaved among first and second output sample values (y_n-1, y_n-2), so that the resulting addition (30; 72; 215; 320) may be carried out with adder circuitry of the same precision as the signal input (x_n) and signal output (y_n). Carry control circuitry (76, 78, 80, 82, 84, 88; 217; 317) is provided to efficiently incorporate magnitude truncation quantization.

Claims

1. A method of determining a feedback value in a digital filter, the feedback value corresponding to a sum of first and second products, the first product corresponding to a first coefficient value times a first output sample value, and the second product corresponding to a second coefficient value times a second output sample value, comprising the steps of:

applying a least significant digit of the first coefficient value to the first output sample value to produce a first partial sum in a sequence of partial sums;

adding the first partial sum to a value determined by applying a least significant digit of the second coefficient value to the second output sample value, to produce a next partial sum in the sequence of partial sums;

shifting the next partial sum according to a difference in order between the least significant digit of the second coefficient value and a next digit of the first coefficient value to produce a shifted next partial sum, and a fractional portion comprised of one or more of least significant bits of the next partial sum;

after the shifting step, adding the shifted next partial sum to a value determined by applying the next digit of the first coefficient value to the first output sample value to produce another next partial sum in the sequence of partial sums;

successively performing the adding, shifting, and adding steps according to the first and second coefficient values, to produce a final partial sum in the sequence of partial sums; and

generating the feedback value based upon the final partial sum.

2. The method of claim 1, wherein the step of generating the feedback value comprises:

generating a carry signal responsive to the sign of the final partial sum and a logical OR operation of the fractional portions from the shifting step; and

adding the final partial sum with the carry signal to produce the feedback value.

3. The method of claim 1, further comprising:

after the step of applying a least significant digit of the first coefficient value to the first output sample value, determining whether the next significant digit of the first coefficient value is of lower order than the least significant digit of the second coefficient value;

responsive to the next significant digit of the first coefficient value being of lower order than the least significant digit of the second coefficient value, then adding the first partial sum to a value determined by applying the next significant digit of the first coefficient value to the first output sample value, to produce a next partial sum;

shifting the next partial sum according to a difference in order between the least significant digit of the first coefficient value and a next digit of the first coefficient value to produce a shifted next partial sum, and a fractional portion comprised of one or more of least significant bits of the next partial sum.

4. The method of claim 1, wherein the first and second coefficient values are in canonic sum digit form.

5. The method of claim 1, wherein the applying steps each comprise:

performing a Booth encoding operation upon a group of bits of a corresponding coefficient value;

controlling a multiply circuit to multiply a corresponding output sample value according to the results of the performing step.

6. The method of claim 1, further comprising:

performing a feed-forward filter operation upon a sequence of input sample values to generate a feed-forward result; and

adding the final partial sum to the carry signal and to the feed-forward result, to produce an output sample value.

7. The method of claim 6, further comprising:

applying a high-pass digital filter to the sequence of input sample values, prior to the step of performing a feed-forward filter operation.

8. The method of claim 1, further comprising:

storing the first and second coefficient values in a memory, prior to the step of applying a least significant digit of the first coefficient value to the first output sample value.

9. An electronic system, comprising:

a signal source for generating digital signals; and

a digital filter, coupled to the signal source, for filtering the digital signals generated by the signal source, by performing a sequence of operations comprising;

applying a least significant digit of the first coefficient value to the first output sample value to produce a first partial sum in a sequence of partial sums;

adding the first partial sum to a value determined by applying a least significant digit of the second coefficient value to the second output sample value, to produce a next partial sum in the sequence of partial sums;

shifting the next partial sum according to a difference in order between the least significant digit of the second coefficient value and a next digit of the first coefficient value to produce a shifted next partial sum, and a fractional portion comprised of one or more of least significant bits of the next partial sum;

after the shifting step, adding the shifted next partial sum to a value determined by applying the next digit of the first coefficient value to the first output sample value to produce another next partial sum in the sequence of partial sums;

successively performing the adding, shifting, and adding steps according to the first and second coefficient values, to produce a final partial sum in the sequence of partial sums; and

generating the feedback value based upon the final partial sum.

10. The system of claim 9, wherein the digital filter comprises:

a programmable logic device.

11. The system of claim 10, wherein the programmable logic device is integrated into an integrated circuit;

and further comprising;

memory for storing a sequence of instructions for controlling the operation of the programmable logic device;

memory for storing input sample values corresponding to the digital signals, and for storing output sample values generated by the digital filter; and

an interface coupled to the signal source for receiving the digital signals.

12. The system of claim 9, wherein the digital filter comprises:

a plurality of adders, each having an input for receiving one of a first output sample value and a second output sample value, and having an output for presenting a partial sum; and

a plurality of shifters, each having an input coupled to the output of one of said adders to receive a corresponding partial sum, having a shift output for presenting a shifted partial sum to an input of one of said plurality of adders, and having a fraction output for presenting a fractional portion of the shifted partial sum, each of the plurality of shifters for shifting the partial sum at its input by a number of bit positions corresponding to a difference in order between successive significant digits of first and second coefficient values;

wherein the plurality of adders and the plurality of shifters are arranged in a sequence corresponding to significant digits of the first and second coefficient values from least significant to most significant, with at least one of the plurality of adders receiving the second output sample value disposed between first and second ones of the plurality of adders receiving the first output sample value.

13. The system of claim 12, wherein the digital filter further comprises:

conjunctive logic having inputs coupled to receive fractional portions of shifted partial sums from each of the plurality of shifters, having an input to receive a sign-bit from the output of a last one of the plurality of adders, and having an output for generating a carry signal;

a final adder, having an input coupled to the conjunctive logic to receive the carry signal, and having an input coupled to receive a final partial sum from the last one of the plurality of adders, for generating a final sum; and

a delay stage, coupled to the output of the final adder, for generating the first and second output sample values.

14. The system of claim 13, further comprising:

a feed-forward portion, having an input coupled to receive a sequence of input sample values, and having an output coupled to the final adder.

15. An electronic device, comprising:

a memory for storing instruction codes, input sample values, and output sample values;

a controller, for receiving instruction codes from the memory and for generating control signals based thereupon; and

a datapath, coupled to the controller, for executing a sequence of instructions responsive to the control signals from the controller, the sequence of instructions comprising;

retrieving first and second coefficient values and first and second output sample values from the memory;

applying a least significant digit of the first coefficient value to the first output sample value to produce a first partial sum in a sequence of partial sums;

adding the first partial sum to a value determined by applying a least significant digit of the second coefficient value to the second output sample value, to produce a next partial sum in the sequence of partial sums;

shifting the next partial sum according to a difference in order between the least significant digit of the second coefficient value and a next digit of the first coefficient value to produce a shifted next partial sum, and a fractional portion comprised of one or more of least significant bits of the next partial sum;

after the shifting step, adding the shifted next partial sum to a value determined by applying the next digit of the first coefficient value to the first output sample value to produce another next partial sum in the sequence of partial sums;

successively performing the adding, shifting, and adding steps according to the first and second coefficient values, to produce a final partial sum in the sequence of partial sums; and

generating a feedback value based upon the final partial sum.

16. The electronic device of claim 15, wherein the operation of generating a feedback value comprises:

generating a carry signal responsive to the sign of the final partial sum and a logical OR operation of the fractional portions from the shifting step; and

adding the final partial sum with the carry signal to produce the feedback value.

17. The electronic device of claim 16, wherein the applying operations each comprise:

performing a Booth encoding operation upon a group of bits of a corresponding coefficient value;

controlling a multiply circuit to multiply a corresponding output sample value according to the results of the performing step.

18. The electronic device of claim 16, wherein the datapath comprises:

a Booth encoded multiplier, for multiplying an operand responsive to control signals from the controller;

an inverting circuit, for inverting the multiplied operand responsive to control signals from the controller;

a shifter, for shifting an operand by a selectable number of bit positions, responsive to control signals from the controller;

carry control circuitry, having an input coupled to the shifter, and having another input for receiving a sign-bit of an operand;

an adder, having a first input coupled to the inverting circuit, having a second input coupled to the shifter, and having a carry input coupled to the carry control circuitry; and

a feedback path from the output of the adder to inputs of the Booth encoded multiplier and shifter.

19. The electronic device of claim 16, wherein the datapath comprises:

a first pipeline, comprising;

a left shifter, for multiplying an operand responsive to control signals from the controller;

an inverting circuit, for inverting the multiplied operand responsive to control signals from the controller;

a first result register, coupled to the inverting circuit;

a second pipeline, comprising;

a right shifter, for shifting an operand by a selectable number of bit positions, responsive to control signals from the controller;

a second result register, coupled to the right shifter;

carry control circuitry, having an input coupled to the shifter, and having another input for receiving a sign-bit of an operand;

an adder, having a first input coupled to the first result register, having a second input coupled to the second result register, and having a carry input coupled to the carry control circuitry;

a shifter, coupled to the output of the adder; and

a feedback path from the output of the shifter to the second pipeline.