Method, system and computer program product for virtual memory support for managing translation look aside buffers with multiple page size support

• US 6,112,285 A
• Filed: 09/23/1997
• Issued: 08/29/2000
• Est. Priority Date: 09/23/1997
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Schimmel, Curt F., Stevens, Luis F., Ganapathy, Narayanan
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): MCLEAN MAYO, KIMBERLY N
• Application Number:
  US08/935,819
• Time in Patent Office: 1,071 Days
• Field of Search: 711/207, 711/206, 711/205, 711/203, 711/208, 711/209, 711/212
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/652 Page size control

Abstract

A system, method and computer program product for virtual memory support for TLBs with multiple page sizes that require only minor revisions to existing operating system code and remains compatible with existing applications. The virtual memory support provided herein is transparent to many existing operating system procedures and application programs. Various page sizes such as 4 KB, 64 KB, 256 KB, 1 MB, 4 MB and 16 MB page sizes can be used by application programs and each process can use multiple page sizes. Base page sized PTEs and data structures associated with physical pages (PFDATs) are maintained. Maintaining PFDATs and PTEs at a base page level facilitates upgrading and downgrading of memory pages. In addition, different processes can have different views of the same data. Support is provided for upgrading and downgrading memory pages. Examples of operating system methods that can be used for virtual memory support for multiple page sized TLBs are provided herein. Such examples include downgrading and upgrading memory pages, large page faulting and prefaulting, large page validation and page table entry setup.

Claims

1. A method for providing virtual memory support for managing translation look aside buffers (TLBs) with multiple page size support for use in a computer system comprising the steps of:

defining a base page size for the computer system;

defining one or more defined large page sizes, each defined large page size being a multiple of said base page size;

maintaining a page frame data structure (PFDAT) for each portion of main memory of said base page size;

maintaining a page table entry (PTE) for each mapped portion of main memory of said base page size; and

faulting in a large memory page, wherein said faulting in step comprises;

(i) determining an appropriate large page size;

(ii) verifying that a region of a virtual address space can accommodate a memory page of said appropriate large page size; and

(iii) setting up a plurality of PTEs, wherein each of the plurality of PTEs is updated to point to a page frame number (PFN) and marked to reflect said appropriate size.

2. A method for providing virtual memory support for managing translation look aside buffers (TLBs) with multiple page size support for use in a computer system comprising the steps of:

defining a base page size for the computer system;

defining one or more defined large page sizes, each defined large page size being a multiple of said base page size;

maintaining a page frame data structure (PFDAT) for each portion of main memory of said base page size;

maintaining a page table entry (PTE) for each mapped portion of main memory of said base page size; and

handling page modify faults on a large memory page, wherein a plurality of base page size portions of said large memory page are tracked for modification;

whereby only each of said plurality of base page size portions that are modified need to be written to file.

3. A system for providing virtual memory support for managing translation look aside buffers (TLBs) with multiple page size support for use in a computer system, comprising:

a base page definer that defines a base page size for the computer system;

a large page definer that defines one or more defined large page sizes, each defined large page size being a multiple of said base page size;

a data structure maintainer that maintains a page frame data structure (PFDAT) for each portion of main memory of said base page size;

a table entry maintainer that maintains a page table entry (PTE) for each mapped portion of main memory of said base page size; and

a faulter that faults in a large memory page, wherein said faulter comprises;

(i) a determiner that determines an appropriate large page size;

(ii) a verifier that verifies that a region of a virtual address space can accommodate a memory page of said appropriate large page size; and

(iii) a PTE setter that sets up a plurality of PTEs, wherein each of the plurality of PTEs is updated to point to a page frame number (PFN) and marked to reflect said appropriate size.

4. A computer program product comprising a computer useable medium having computer program logic stored therein, said computer program logic for providing virtual memory support for managing translation look aside buffers (TLBs) with multiple page size support for use in a computer system, comprising:

a base page definer that enables the computer to define a base page size for the computer system;

a large page definer that enables the computer to define one or more defined large page sizes, each defined large page size being a multiple of said base page size;

a data structure maintainer that enables the computer to maintain a page frame data structure (PFDAT) for each portion of main memory of said base page size;

a table entry maintainer that enables the computer to maintain a page table entry (PTE) for each mapped portion of main memory of said base page size; and

a faulter that enables the computer to fault in a large memory page, wherein said faulter comprises;

(i) a determiner that enables the computer to determine an appropriate large page size;

(ii) a verifier that enables the computer to verify that a region of a virtual address space can accommodate a memory page of said appropriate large page size; and

(iii) a PTE setter that enables the computer to set up a plurality of PTEs, wherein each of the plurality of PTEs is updated to point to a page frame number (PFN) and marked to reflect said appropriate size.

5. A system for providing virtual memory support for managing translation look aside buffers (TLBs) with multiple page size support for use in a computer system, comprising:

a base page definer that defines a base page size for the computer system;

a large page definer that defines one or more defined large page sizes, each defined large page size being a multiple of said base page size;

a data structure maintainer that maintains a page frame data structure (PFDAT) for each portion of main memory of said base page size;

a table entry maintainer that maintains a page table entry (PTE) for each mapped portion of main memory of said base page size; and

a fault handler that handles page modify faults on a large memory page, wherein a plurality of base page size portions of said large memory page are tracked for modification;

whereby only each of said plurality of base page size portions that are modified need to be written to file.

6. A computer program product comprising a computer useable medium having computer program logic stored therein, said computer program logic for providing virtual memory support for managing translation look aside buffers (TLBs) with multiple page size support for use in a computer system, comprising:

a base page definer that enables the computer to define a base page size for the computer system;

a large page definer that enables the computer to define one or more defined large page sizes, each defined large page size being a multiple of said base page size;

a data structure maintainer that enables the computer to maintain a page frame data structure (PFDAT) for each portion of main memory of said base page size;

a table entry maintainer that enables the computer to maintain a page table entry (PTE) for each mapped portion of main memory of said base page size; and

fault handler that enables the computer to handle page modify faults on a large memory page, wherein a plurality of base page size portions of said large memory page are tracked for modification;

whereby only each of said plurality of base page size portions that are modified need to be written to file.