High frequency pipeline decoupling queue with non-overlapping read and write signals within a single clock cycle
First Claim
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1. A method for expediting the processing of a plurality of instructions in a processor, the method comprising:
- a. providing a plurality of pipeline units to process said plurality of instructions, wherein each of said plurality of pipeline units has a plurality of pipe stages; and
b. providing a decoupling queue to decouple at least one of said pipe stages from another, wherein said decoupling queue generates non-overlapping read and write signals to support corresponding read and write operations within a single clock cycle of said processor.
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Abstract
A method and apparatus for expediting the processing of a plurality of instructions in a processor is disclosed. In one embodiment, said processor has a plurality of pipeline units to process a plurality of instructions. Each of said pipeline units has a plurality of pipe stages. Further, a decoupling queue is provided to decouple at least one of said pipe stages from another, wherein said decoupling generates non-overlapping read and write signals to support corresponding read and write operations within a single clock cycle of said processor.
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Citations
27 Claims
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1. A method for expediting the processing of a plurality of instructions in a processor, the method comprising:
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a. providing a plurality of pipeline units to process said plurality of instructions, wherein each of said plurality of pipeline units has a plurality of pipe stages; and b. providing a decoupling queue to decouple at least one of said pipe stages from another, wherein said decoupling queue generates non-overlapping read and write signals to support corresponding read and write operations within a single clock cycle of said processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A processor comprising:
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a plurality of pipeline units for processing a plurality of instructions, wherein each of said plurality of pipeline units has a plurality of pipe stages; and a decoupling queue for decoupling at least one of said pipe stages from another, wherein said decoupling queue generates non-overlapping read and write signals to support corresponding read and write operations within a single clock cycle of said processor. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A computer system comprising:
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a processor including, a plurality of pipeline units for processing a plurality of instructions, wherein each of said plurality of pipeline units has a plurality of pipe stages; and a decoupling queue for decoupling at least one of said pipe stages from another, wherein said decoupling queue generates non-overlapping read and write signals to support corresponding read and write operations within a single clock cycle of said processor; and a bus element, coupled to a storage device and said processor, wherein said storage device contains an operating system. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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Specification