High frequency pipeline decoupling queue with non-overlapping read and write signals within a single clock cycle

• US 6,112,295 A
• Filed: 09/24/1998
• Issued: 08/29/2000
• Est. Priority Date: 09/24/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Vaid, Kushagra V., Bhamidipati, Sriram
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US09/160,364
• Time in Patent Office: 705 Days
• Field of Search: 711/109, 711/110, 711/167, 712/23, 712/219
• US Class Current: 712/219
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3871 Asynchronous instruction pipeline, e.g. using handshake signals between stages

Abstract

A method and apparatus for expediting the processing of a plurality of instructions in a processor is disclosed. In one embodiment, said processor has a plurality of pipeline units to process a plurality of instructions. Each of said pipeline units has a plurality of pipe stages. Further, a decoupling queue is provided to decouple at least one of said pipe stages from another, wherein said decoupling generates non-overlapping read and write signals to support corresponding read and write operations within a single clock cycle of said processor.

Claims

1. A method for expediting the processing of a plurality of instructions in a processor, the method comprising:

a. providing a plurality of pipeline units to process said plurality of instructions, wherein each of said plurality of pipeline units has a plurality of pipe stages; and

b. providing a decoupling queue to decouple at least one of said pipe stages from another, wherein said decoupling queue generates non-overlapping read and write signals to support corresponding read and write operations within a single clock cycle of said processor.

2. The method according to claim 1, wherein said decouplig queue in (b) further comprises:

a control logic unit;

a timing generation unit; and

a data storage unit.

3. The method according to claim 2, wherein said timing generation unit generates said non-overlapping write signal for triggering said write operation within said single clock cycle;

generates said non-overlapping read signal for triggering said read operation within said same single clock cycle; and

ensures said write and read signals remain active for a minimum duration to complete said corresponding write and read operations and satisfy a subsequent logic stage'"'"'s setup time requirement.

4. The method according to claim 1, wherein a sequence of performing said write and read operations is interchangeable.

5. The method according to claim 1, wherein said write and read operations can be performed on a same entry of said data storage unit.

6. The method according to claim 4, wherein said control logic unit determines said sequence of said write and read operations;

and

instructs said timing generation unit to generate said write and read signals according to said sequence.

7. The method according to claim 3, wherein said timing generation unit generates a first signal, either said write signal or said read signal and a second signal, either said write signal or said read signal wherein

said first signal is triggered by a rising edge of a clock signal of said processor;

and

said second signal is triggered by a falling edge of said first signal.

8. The method according to claim 2, wherein said single clock cycle of said processor is small;

and

said data storage unit has a small number of data entries, but each of said data entries can store large data values.

9. The method according to claim 2, wherein said data storage unit is a registry file.

10. A processor comprising:

a plurality of pipeline units for processing a plurality of instructions, wherein each of said plurality of pipeline units has a plurality of pipe stages; and

a decoupling queue for decoupling at least one of said pipe stages from another, wherein said decoupling queue generates non-overlapping read and write signals to support corresponding read and write operations within a single clock cycle of said processor.

11. The processor according to claim 10, wherein said decoupling queue further comprises:

a control logic unit;

a timing generation unit; and

a data storage unit.

12. The processor according to claim 11, wherein said timing generation unit generates said non-overlapping write signal for triggering said write operation within said single clock cycle;

generates said non-overlapping read signal for triggering said read operation within said same single clock cycle; and

ensures said write and read signals remain active for a minimum duration to complete said corresponding write and read operations and satisfy a subsequent logic stage'"'"'s setup time requirement.

13. The processor according to claim 10, wherein a sequence of performing said write and read operations is interchangeable.

14. The processor according to claim 10, wherein said write and read operations can be performed on a same entry of said data storage unit.

15. The processor according to claim 13, wherein said control logic unit determines said sequence of said write and read operations;

and

instructs said timing generation unit to generate said write and read signals according to said sequence.

16. The processor according to claim 12, wherein said timing generation unit generates a first signal, either said write signal or said read signal and a second signal, either said write signal or said read signal wherein

said first signal is triggered by a rising edge of a clock signal of said processor;

and

said second signal is triggered by a falling edge of said first signal.

17. The processor according to claim 11, wherein said single clock cycle of said processor is small;

and

said data storage unit has a small number of data entries, but each of said data entries can store large data values.

18. The processor according to claim 11, wherein said data storage unit is a register file.

19. A computer system comprising:

a processor including,

a plurality of pipeline units for processing a plurality of instructions, wherein each

of said plurality of pipeline units has a plurality of pipe stages; and

a decoupling queue for decoupling at least one of said pipe stages from another, wherein said decoupling queue generates non-overlapping read and write signals to support corresponding read and

write operations within a single clock cycle of said processor; and

a bus element, coupled to a storage device and said processor, wherein said storage device contains an operating system.

20. The computer system according to claim 19, wherein said processor includes said decoupling queue which further comprises:

a control logic unit;

a timing generation unit; and

a data storage unit.

21. The computer system according to claim 20, wherein said decoupling queue includes said timing generation unit which

generates said non-overlapping write signal for triggering said write operation within said single clock cycle;

generates said non-overlapping read signal for triggering said read operation within said same single clock cycle; and

ensures said write and read signals remain active for a minimum duration to complete said corresponding write and read operations and satisfy a subsequent logic stage'"'"'s setup time requirement.

22. The computer system according to claim 21, wherein said decoupling queue can perform a sequence of said write and read operations interchangeably.

23. The computer system according to claim 19, wherein said write and read operations can perform on a same entry of said data storage unit.

24. The computer system according to claim 22, wherein said decoupling queue includes said control logic unit which

determines said sequence of said write and read operations;

and

instructs said timing generation unit to generate said write and read signals according to said sequence.

25. The computer system according to claim 24, wherein said decoupling queue includes said timing generation unit which

generates a first signal, either said write signal or said read signal and a second signal,

either said write signal or said read signal wherein

said first signal is triggered by a rising edge of a clock signal of said processor;

and

said second signal is triggered by a falling edge of said first signal.

26. The computer system according to claim 20, wherein

said single clock cycle of said processor is small;

and

said self-timed queue includes said data storage unit which has a small number of data entries, but each of said data entries can store large data values.

27. The computer system according to claim 20, wherein

said self-timed queue includes said data storage unit which is a register file.