Method for managing an instruction execution pipeline during debugging of a data processing system

• US 6,112,298 A
• Filed: 11/19/1997
• Issued: 08/29/2000
• Est. Priority Date: 12/20/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Seshan, Natarajan, Deao, Douglas E.
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US08/974,742
• Time in Patent Office: 1,014 Days
• Field of Search: 710/260, 712/227
• US Class Current: 712/227
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 11/3648 using additional hardware

Abstract

A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.

Claims

1. A method for debugging a data processing system, said data processing system having a processor which has an instruction execution pipeline, comprising the steps of:

executing system code in said processor instruction execution pipeline in a normal operational manner to initiate a plurality of overlapping operations in said instruction pipeline;

halting said normal operation of said processor in a manner that saves a plurality of states representative of said overlapping operations;

executing debug code in said processor instruction execution pipeline to perform a debug operation on said processor; and

continuing execution of said system code in said processor instruction execution pipeline by restoring said plurality of states in a manner that no extraneous operations occur within said data processing system; and

wherein the step of halting further comprises;

halting the processor on a phase boundary before at least one of the plurality of overlapping operations is complete and then storing as a first state first contents of a plurality of memory elements within the processor;

executing one phase of the instruction execution pipeline and then storing as a second state second contents of the plurality of memory elements; and

repeating the step of executing one phase and then storing another state until all of the plurality of overlapping operations is complete.

2. The method of claim 1, wherein the step of executing debug code further comprises:

introducing at least one processor instruction into the processor instruction execution pipeline to access a first memory internal to the processor in a normal operational manner to obtain first data from the first memory and storing the first data in a first memory element of the plurality of memory elements; and

transferring the first data from the first memory element to a test port on the processor.

3. The method of claim 2, wherein the step of continuing execution of said system code further comprises:

restoring said first contents from said saved first state to said plurality of memory elements within said processor and then executing one phase of said instruction execution pipeline;

restoring said second contents from said saved second state to said plurality of memory elements within said processor and then executing one phase of said instruction execution pipeline; and

repeating said step of restoring memory element contents and then executing one phase of said pipeline until all of said plurality of states have been restored.

4. The method of claim 3, wherein the steps of halting, executing debug code, and continuing execution of said system code causes no extraneous memory cycles within said data processing system.

5. The method of claim 4, wherein the steps of halting, executing debug code, and continuing execution of said system code causes no extraneous I/O cycles within said data processing system.

6. The method of claim 5 wherein the steps of executing one phase and then storing another state further comprise transferring said memory element contents of said plurality of memory elements via a serial scan path to said test port on said processor.

7. The method of claim 6 wherein the step of halting normal operation further comprises prohibiting the execution of any instruction which had not entered an operand acquisition phase of said execution pipeline prior to said halt step.

8. The method of claim 7 wherein the steps of restoring contents to said plurality of memory elements further comprises performing said step of halting again if a condition indicative of a halt request is detected.

9. A method for debugging a processor within a data processing system, the processor having an instruction execution pipeline, comprising the steps of:

executing a sequence of instructions in the processor instruction execution pipeline in a normal operational manner to initiate a plurality of partially executed instructions in a plurality of stages of the instruction pipeline;

halting the normal operation of the processor in response to a debug event such that the plurality of partially executed instructions is maintained and then saving a first state representative of the instruction execution pipeline;

inhibiting fetching of a new instruction;

single stepping the instruction execution pipeline one pipeline phase and then saving a second state representative of the instruction pipeline; and

repeating the step of single stepping the instruction execution pipeline one pipeline phase and saving another state representative of the instruction pipeline until the instruction execution pipeline is flushed of partially executed instructions.

10. The method of claim 9, further comprising the step of annulling a first portion of the plurality of partially executed instructions that have not yet entered a selected stage in the instruction execution pipeline.

11. The method of claim 10, wherein a second portion of the plurality of partially executed instructions that have entered the selected stage of the instruction execution pipeline are not annulled.

12. The method of claim 9, wherein the step of single stepping one pipeline phase further comprises waiting a non-specific amount of time while a memory access is completed.

13. The method of claim 9, wherein the step of single stepping one pipeline phase further comprises waiting a non-specific amount of time while a plurality of memory accesses are completed.

14. The method of claim 9, wherein the step of saving a first state comprises saving the contents of a plurality of registers associated with the instruction execution pipeline.

15. The method of claim 11, wherein the second state includes data provided by an access to a data memory in response to one of the second portion of partially executed instructions.

16. The method of claim 9, wherein the debug event is the detecting of a software breakpoint instruction.

17. The method of claim 15, further comprising the steps of:

restoring a first portion of the first state representative of the instruction execution pipeline;

single stepping the instruction execution pipeline one pipeline phase and then restoring a second portion of the first state representative of the instruction pipeline; and

repeating the step of single stepping the instruction execution pipeline one pipeline phase and restoring another state representative of the instruction pipeline until the instruction execution pipeline is restored with the plurality of partially executed instructions.

18. The method of claim 17, wherein the step of repeating annuls the second portion of partially executed instructions so that a memory access requested by one of the second portion of partially executed instructions is not performed;

and

wherein the first portion of partially executed instructions is not annulled.

19. The method of claim 18, further comprising the step of enabling fetching of new instructions and starting the normal operation of the processor;

and

wherein a redundant instruction fetch is not performed and a redundant data memory access is not performed by the plurality of partially executed instructions.

20. A data processing system comprising a microprocessor instruction, the microprocessor comprising:

an instruction register;

an instruction execution pipeline connected to the instruction register for executing system code from the instruction register, operable to initiate a plurality of overlapping operations in the instruction execution pipeline;

emulation circuitry connected to the instruction execution pipeline and to the instruction register for halting the normal operation of the processor, the emulation circuitry operable to halt the instruction execution pipeline on a phase boundary before at least one of the plurality of overlapping operations is complete and then store as a first state first contents of a plurality of memory elements within the processor;

the emulation circuitry further operable to inhibit instruction fetching in the instruction register and to cause the instruction execution pipeline to advance on one phase and to then store as a second state second contents of the plurality of memory elements; and

the emulation circuitry further operable to repeat the steps of executing one phase and then storing another state until the system code instructions are flushed from the instruction execution pipeline.

21. The data processing system of claim 20, wherein the emulation circuitry is further operable to restore the first state of the contents of the instruction pipeline into the instruction pipeline before normal operation of the processor is resumed.

22. The data processing system of claim 21, further comprising program memory for holding program instructions connected to the microprocessor.

23. The data processing system of claim 22, wherein the instruction execution pipeline is further operable to resume execution of system code in a normal operational manner after executing the first sequence of debug code without refetching an instruction from the program memory.

24. The data processing system of claim 23, further comprising a plurality of peripheral devices connected to the microprocessor.