Computer system with system ROM including serial-access PROM coupled to an auto-configuring memory controller and method of shadowing BIOS code from PROM

• US 6,112,303 A
• Filed: 02/18/1999
• Issued: 08/29/2000
• Est. Priority Date: 12/20/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Stancil, Charles J.
• Primary Examiner(s): Palys, Joseph E.
• Assistant Examiner(s): Mai, Rijue
• Application Number:
  US09/252,431
• Time in Patent Office: 558 Days
• Field of Search: 713/1, 713/2, 713/100, 395/712, 395/700, 395/500, 395/200.51, 364/900, 709/220, 709/221, 709/222, 710/8, 710/9, 710/10, 710/101
• US Class Current: 713/2
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

A computer system having a processor is provided with a memory controller serially coupled to a serial-access programmable ROM (PROM) through the serial PROM interface of the controller. The random-access memory controller randomly accesses the BIOS code in the serial PROM during power-up of the computer system in response to read requests from the CPU. If the memory controller cannot immediately process the read requests from the CPU, the controller creates wait states for the CPU. The auto-configuring memory controller sequentially accesses the entire BIOS code in the serial PROM during power-up and prior to the running of the CPU, and copies it to a portion of base memory eliminating random accesses to the PROM.

Claims

1. A computer system comprising:

a processor;

an internal serial-access programmable read-only-memory (PROM) for storing BIOS code;

a memory controller coupled to said processor and serially and directly coupled to said PROM for addressing said PROM and for loading the BIOS code from said PROM comprising;

a serial PROM interface coupling said memory controller and said serial PROM allowing communication between said controller and said PROM; and

serial PROM interface control logic for controlling said serial PROM interface; and

an internal parallel-access programmable read-only-memory coupled to the memory controller.

2. The computer system of claim 1, wherein said memory controller buffers data allowing for burstable CPU accesses to said memory controller.

3. The computer system of claim 1, wherein said memory controller fetches data from said serial-access PROM prior to a CPU read request.

4. The computer system of claim 1, wherein said serial-access PROM is a serial electrically erasable programmable read-only-memory (EEPROM).

5. The computer system of claim 1, wherein said serial-access PROM has a memory capacity of 32 kilobytes (KB).

6. The computer system of claim 1, further comprising:

firmware stored in said serial-access PROM.

7. The computer system of claim 6, wherein said firmware copies the BIOS code in said PROM to said memory controller.

8. The computer system of claim 6, said system having an operating system, wherein the firmware loads said operating system.

9. The computer system of claim 6, further comprising:

an operating system loaded by the firmware.

10. The computer system of claim 1, further comprising:

an internal mass storage device for storing BIOS code.

11. The computer system of claim 10, wherein a portion of the BIOS code is stored in said serial-access PROM, and a portion of the BIOS code is stored in said internal mass storage device.

12. The computer system of claim 1, wherein said memory controller receiving processor addresses and read-request signals from said processor comprises:

wait state logic for asserting wait states into the cycles of said processor; and

PROM address mapping logic for mapping said processor addresses to serial PROM addresses permitting random access to said serial PROM.

13. The computer system of claim 12, wherein said serial PROM interface uses a serial protocol.

14. The computer system of claim 12, wherein said serial PROM interface has a write-protect function.

15. The computer system of claim 12, wherein said serial PROM interface includes:

a set of pins for inputting and outputting clock signals, inputting and outputting data signals, and inputting write-protect signals.

16. The computer system of claim 12, wherein said serial PROM interface control logic comprises:

logic for generating clock signals;

logic for controlling data signals; and

logic for generating write-protect signals.

17. The computer system of claim 1, said system having base memory, wherein said memory controller comprises:

auto-configuring/base memory logic for auto-detecting the base memory in said computer system, and then auto-configuring said memory controller to copy the contents of said serial PROM into a portion of said base memory.

18. The computer system of claim 17, wherein said serial-access PROM uses a page-read mode.

19. The computer system of claim 17, wherein said serial PROM interface uses a serial protocol.

20. A random-access memory controller coupled to a processor of a computer system, said controller further directly and serially coupled to a internal serial-access programmable read-only-memory and coupled to an internal parallel-access programmable read-only-memory, comprising:

wait state logic for asserting wait states into the cycles of a processor;

PROM address mapping logic for mapping said processor addresses to PROM addresses;

a serial PROM interface coupling a memory controller and an internal serial PROM allowing communication between said memory controller and said internal serial PROM; and

serial PROM interface control logic for controlling said serial PROM interface.

21. The memory controller of claim 20, wherein said serial PROM interface uses an I² C protocol.

22. The memory controller of claim 20, wherein said serial PROM interface has a write-protect function.

23. The memory controller of claim 20, wherein said serial PROM interface includes:

a set of pins for inputting and outputting clock signals inputting and outputting data signals, and inputting write-protect signals.

24. The memory controller of claim 20, wherein said serial PROM interface control logic comprises:

logic for generating clock signals;

logic for controlling data signals; and

logic for generating write-protect signals.

25. The memory controller of claim 20, wherein said memory controller buffers data allowing for burstable CPU accesses to said controller.

26. The memory controller of claim 20, wherein said memory controller fetches data from said serial-access PROM prior to a CPU read request.

27. A computer system adapted for loading BIOS code from an internal serial-access programmable read-only-memory (PROM), comprising:

a processor;

a internal serial-access PROM to store BIOS code; and

a memory controller coupled to the processor and directly and serially coupled to the internal serial-access PROM, comprising;

PROM addressing mapping logic to map between processor addresses and PROM addresses;

a serial PROM interface to allow communication between the memory controller and the internal serial-access PROM; and

a serial PROM interface control logic to control the serial PROM interface; and

an internal parallel-access programmable read-only-memory coupled to the memory controller.

28. The computer system of claim 27, further comprising:

a serial bus between the internal serial-access PROM and the memory controller.

29. The computer system of claim 28, the internal serial-access PROM comprising:

firmware to copy the BIOS code to the memory controller over the serial bus.