Computer watchdog timer

• US 6,112,320 A
• Filed: 10/29/1997
• Issued: 08/29/2000
• Est. Priority Date: 10/29/1997
• Status: Expired due to Fees

• Current Assignee: Ghing-Hsin Dien
• Original Assignee: Ghing-Hsin Dien
• Inventors: Dien, Ghing-Hsin
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): ELISCA, PIERRE E
• Application Number:
  US08/960,312
• Time in Patent Office: 1,035 Days
• Field of Search: 714/45, 714/51, 714/55, 714/56, 714/23, 364/267.9
• US Class Current: 714/51
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

A watchdog timer for a computer with a CPU and a peripheral controller. The watchdog timer includes a program in the peripheral controller and a corresponding program in the peripheral interrupt service routine of the CPU. When the watchdog timer function is enabled, the peripheral controller will interrupt the CPU periodically and check the response from the CPU. If the CPU is not responding, or wrong data is returned from the CPU, the peripheral controller will generate a reset signal to reset the CPU and reboot the system.

Claims

1. A watchdog timer for a computer having a central processing unit and a peripheral controller comprising:

a. a watchdog program, executing on a micro-code program on said peripheral controller, which periodically interrupts and sends a watchdog check command to said central processing unit of said computer; and

b. a watchdog interrupt service routine, executing on said central processing unit of said computer, which responds to said interrupt and said watchdog check command with a predefined response;

wherein said peripheral controller and watchdog program can reset said computer if said predefined response is not received from said watchdog interrupt service routine executing on said central processing unit of said computer.

2. The watchdog timer of claim 1 wherein said central processing unit and said peripheral controller are coupled via a communications bus and wherein said watchdog check command and said predefined response are communicated over said bus.

3. The watchdog timer of claim 1 wherein said peripheral controller has an interrupt output and said central processing unit has an interrupt input and wherein said interrupt output of said peripheral controller is coupled to said interrupt input of said central processing unit.

4. The watchdog timer of claim 1 wherein said peripheral controller has a reset output and said central processing unit has a reset input and wherein said reset output of said peripheral controller is coupled to said reset input of said central processing unit.

5. The watchdog timer of claim 1 further comprising a timeout function wherein said watchdog program resets said computer if said predetermined response is not received from said central processing unit of said computer within a predetermined time period.

6. The watchdog timer of claim 1 wherein said watchdog program can be disabled.

7. The watchdog timer of claim 1 further comprising a second watchdog program, executing on said central processing unit of said computer, which periodically sends a watchdog peripheral check command to said watchdog program executing on said peripheral controller, wherein said watchdog program executing on said peripheral controller responds to said watchdog peripheral check command with a predetermined response and wherein said second watchdog program executing on said central processing unit of said computer can reset said peripheral controller if said response is not received from said watchdog program executing on said peripheral controller.

8. The watchdog timer of claim 7 wherein said central processing unit and said peripheral controller are coupled via a communications bus and wherein said watchdog check command and said predefined response are communicated over said bus.

9. The watchdog timer of claim 7 wherein said peripheral controller has an interrupt output and said central processing unit has an interrupt input and wherein said interrupt output of said peripheral controller is coupled to said interrupt input of said central processing unit.

10. The watchdog timer of claim 7 wherein said peripheral controller has a reset output and said central processing unit has a reset input and wherein said reset output of said peripheral controller is coupled to said reset input of said central processing unit.

11. The watchdog timer of claim 7 further comprising a timeout function wherein said watchdog program resets said computer if said predetermined response is not received from said central processing unit of said computer within a predetermined time period.

12. The watchdog timer of claim 7 further comprising a timeout function wherein said second watchdog program resets said peripheral controller if said predetermined response is not received from said peripheral controller with a predetermined time period.

13. The watchdog timer of claim 7 wherein said watchdog program and said second watchdog program can be disabled.