Method to avoid copper contamination on the sidewall of a via or a dual damascene structure
First Claim
1. A method of preventing copper contamination of an intermetal dielectric layer during via or dual damascene etching in the fabrication of an integrated circuit device comprising:
- forming a first copper metallization in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying said first copper metallization and overlying said dielectric layer;
planarizing said first copper metallization;
etching said first copper metallization to form a recess below the surface of said dielectric layer;
removing said barrier metal layer overlying said dielectric layer;
depositing a conductive capping layer overlying said first copper metallization within said recess and overlying said dielectric layer;
coating a spin-on material overlying said conductive capping layer;
etching back said spin-on material and said conductive capping layer over said dielectric layer;
thereafter removing all of said spin-on material leaving said conductive capping layer only over said first copper metallization in said recess;
depositing said intermetal dielectric layer overlying said dielectric layer and said conductive capping layer overlying said first copper metallization;
etching said via or dual damascene opening through said intermetal dielectric layer to said conductive capping layer wherein said conductive capping layer prevents copper contamination of said intermetal dielectric layer during said etching; and
filling said via or dual damascene opening with a metal layer to complete electrical connections in the fabrication of said integrated circuit device.
1 Assignment
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Accused Products
Abstract
A new method to prevent copper contamination of the intermetal dielectric layer during via or dual damascene etching by forming a capping layer over the first copper metallization is described. A first copper metallization is formed in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying the first copper metallization and overlying the dielectric layer. The first copper metallization is planarized, then etched to form a recess below the surface of the dielectric layer. A conductive capping layer is deposited overlying the first copper metallization within the recess and overlying the dielectric layer. The conductive capping layer is removed except over the first copper metallization within the recess using one of several methods. An intermetal dielectric layer is deposited overlying the dielectric layer and the conductive capping layer overlying the first copper metallization. A via or dual damascene opening is etched through the intermetal dielectric layer to the conductive capping layer wherein the conductive capping layer prevents copper contamination of the intermetal dielectric layer during etching. The via or dual damascene opening is filled with a metal layer to complete electrical connections in the fabrication of an integrated circuit device.
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Citations
28 Claims
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1. A method of preventing copper contamination of an intermetal dielectric layer during via or dual damascene etching in the fabrication of an integrated circuit device comprising:
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forming a first copper metallization in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying said first copper metallization and overlying said dielectric layer; planarizing said first copper metallization; etching said first copper metallization to form a recess below the surface of said dielectric layer; removing said barrier metal layer overlying said dielectric layer; depositing a conductive capping layer overlying said first copper metallization within said recess and overlying said dielectric layer; coating a spin-on material overlying said conductive capping layer; etching back said spin-on material and said conductive capping layer over said dielectric layer; thereafter removing all of said spin-on material leaving said conductive capping layer only over said first copper metallization in said recess; depositing said intermetal dielectric layer overlying said dielectric layer and said conductive capping layer overlying said first copper metallization; etching said via or dual damascene opening through said intermetal dielectric layer to said conductive capping layer wherein said conductive capping layer prevents copper contamination of said intermetal dielectric layer during said etching; and filling said via or dual damascene opening with a metal layer to complete electrical connections in the fabrication of said integrated circuit device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of preventing copper contamination of an intermetal dielectric layer during via or dual damascene etching in the fabrication of an integrated circuit device comprising:
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forming a first copper metallization in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying said first copper metallization and overlying said dielectric layer; planarizing said first copper metallization; etching said first copper metallization to form a recess below the surface of said dielectric layer; removing said barrier metal layer overlying said dielectric layer; depositing a conductive capping layer overlying said first copper metallization within said recess and overlying said dielectric layer; forming a mask over said first copper metallization area and etching away said conductive capping layer where it is not covered by said mask leaving said conductive capping layer only over said first copper metallization in said recess; thereafter removing said mask; depositing said intermetal dielectric layer overlying said dielectric layer and said conductive capping layer overlying said first copper metallization; etching said via or dual damascene opening through said intermetal dielectric layer to said conductive capping layer wherein said conductive capping layer prevents copper contamination of said intermetal dielectric layer during said etching; and filling said via or dual damascene opening with a metal layer to complete electrical connections in the fabrication of said integrated circuit device. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A method of preventing copper contamination of an intermetal dielectric layer during via or dual damascene etching in the fabrication of an integrated circuit device comprising:
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forming a first copper metallization in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying said first copper metallization and overlying said dielectric layer; planarizing said first copper metallization; etching said first copper metallization to form a recess below the surface of said dielectric layer; depositing a conductive capping layer overlying said first copper metallization within said recess and overlying said dielectric layer; partially polishing away said conductive capping layer wherein said conductive capping layer over said first copper metallization is thicker than said conductive capping layer over said dielectric layer; thereafter etching back said conductive capping layer and said barrier metal layer overlying said dielectric layer leaving said conductive capping layer only over said first copper metallization within said recess; depositing said intermetal dielectric layer overlying said dielectric layer and said conductive capping layer overlying said first copper metallization; etching said via or dual damascene opening through said intermetal dielectric layer to said conductive capping layer wherein said conductive capping layer prevents copper contamination of said intermetal dielectric layer during said etching; and filling said via or dual damascene opening with a metal layer to complete electrical connections in the fabrication of said integrated circuit device. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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Specification