Method to avoid copper contamination on the sidewall of a via or a dual damascene structure

• US 6,114,243 A
• Filed: 11/15/1999
• Issued: 09/05/2000
• Est. Priority Date: 11/15/1999
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Inventors: Chool, Simon, Gupta, Subhash, Zhou, Mei-Sheng, Ho, Kwok Keung Paul
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US09/439,361
• Time in Patent Office: 295 Days
• Field of Search: 438/638, 438/633, 438/648, 438/656, 438/685, 438/687, 438/666, 438/668, 438/669, 438/671, 438/672
• US Class Current: 438/687
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material

Abstract

A new method to prevent copper contamination of the intermetal dielectric layer during via or dual damascene etching by forming a capping layer over the first copper metallization is described. A first copper metallization is formed in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying the first copper metallization and overlying the dielectric layer. The first copper metallization is planarized, then etched to form a recess below the surface of the dielectric layer. A conductive capping layer is deposited overlying the first copper metallization within the recess and overlying the dielectric layer. The conductive capping layer is removed except over the first copper metallization within the recess using one of several methods. An intermetal dielectric layer is deposited overlying the dielectric layer and the conductive capping layer overlying the first copper metallization. A via or dual damascene opening is etched through the intermetal dielectric layer to the conductive capping layer wherein the conductive capping layer prevents copper contamination of the intermetal dielectric layer during etching. The via or dual damascene opening is filled with a metal layer to complete electrical connections in the fabrication of an integrated circuit device.

Claims

1. A method of preventing copper contamination of an intermetal dielectric layer during via or dual damascene etching in the fabrication of an integrated circuit device comprising:

forming a first copper metallization in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying said first copper metallization and overlying said dielectric layer;

planarizing said first copper metallization;

etching said first copper metallization to form a recess below the surface of said dielectric layer;

removing said barrier metal layer overlying said dielectric layer;

depositing a conductive capping layer overlying said first copper metallization within said recess and overlying said dielectric layer;

coating a spin-on material overlying said conductive capping layer;

etching back said spin-on material and said conductive capping layer over said dielectric layer;

thereafter removing all of said spin-on material leaving said conductive capping layer only over said first copper metallization in said recess;

depositing said intermetal dielectric layer overlying said dielectric layer and said conductive capping layer overlying said first copper metallization;

etching said via or dual damascene opening through said intermetal dielectric layer to said conductive capping layer wherein said conductive capping layer prevents copper contamination of said intermetal dielectric layer during said etching; and

filling said via or dual damascene opening with a metal layer to complete electrical connections in the fabrication of said integrated circuit device.

2. The method according to claim 1 wherein said barrier metal layer comprises one of the group containing:

tantalum, tantalum compounds, titanium, titanium compounds, tungsten, and tungsten compounds.

3. The method according to claim 1 wherein said step of planarizing said first copper metallization comprises polishing said first copper metallization using chemical mechanical polishing (CMP) wherein said barrier metal layer is used as a CMP stop layer.

4. The method according to claim 1 wherein said recess is formed by a wet etch method.

5. The method according to claim 4 wherein said wet etch method comprises CH₂ COOH/NH₄ F or DMSO/CCl₄ chemistry.

6. The method according to claim 1 wherein said step of removing said barrier metal layer comprises etching selective to said barrier metal layer using Cl or F plasma.

7. The method according to claim 1 wherein said conductive capping layer comprises one of the group containing:

tantalum, tantalum compounds, titanium, titanium compounds, tungsten, and tungsten compounds.

8. The method according to claim 1 wherein said step of etching back said spin-on material and said conductive capping layer over said dielectric layer comprises a Cl or F plasma etch.

9. The method according to claim 1 wherein said step of removing said spin-on material comprises stripping in an O₂ plasma or forming gas plasma.

10. The method according to claim 1 wherein said step of removing said barrier metal layer is performed before said step of depositing said conductive capping layer.

11. A method of preventing copper contamination of an intermetal dielectric layer during via or dual damascene etching in the fabrication of an integrated circuit device comprising:

forming a first copper metallization in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying said first copper metallization and overlying said dielectric layer;

planarizing said first copper metallization;

etching said first copper metallization to form a recess below the surface of said dielectric layer;

removing said barrier metal layer overlying said dielectric layer;

depositing a conductive capping layer overlying said first copper metallization within said recess and overlying said dielectric layer;

forming a mask over said first copper metallization area and etching away said conductive capping layer where it is not covered by said mask leaving said conductive capping layer only over said first copper metallization in said recess;

thereafter removing said mask;

depositing said intermetal dielectric layer overlying said dielectric layer and said conductive capping layer overlying said first copper metallization;

etching said via or dual damascene opening through said intermetal dielectric layer to said conductive capping layer wherein said conductive capping layer prevents copper contamination of said intermetal dielectric layer during said etching; and

filling said via or dual damascene opening with a metal layer to complete electrical connections in the fabrication of said integrated circuit device.

12. The method according to claim 11 wherein said barrier metal layer comprises one of the group containing:

tantalum, tantalum compounds, titanium, titanium compounds, tungsten, and tungsten compounds.

13. The method according to claim 11 wherein said step of planarizing said first copper metallization comprises polishing said first copper metallization using chemical mechanical polishing (CMP) wherein said barrier metal layer is used as a CMP stop layer.

14. The method according to claim 11 wherein said recess is formed by a wet etch method.

15. The method according to claim 14 wherein said wet etch method comprises CH₂ COOH/NH₄ F or DMSO/CCl₄ chemistry.

16. The method according to claim 11 wherein said step of removing said barrier metal layer comprises etching selective to said barrier metal layer using Cl or F plasma.

17. The method according to claim 11 wherein said conductive capping layer comprises one of the group containing:

tantalum, tantalum compounds, titanium, titanium compounds, tungsten, and tungsten compounds.

18. The method according to claim 11 wherein said step of forming said mask comprises using a reverse of a mask used to form said first copper metallization area.

19. The method according to claim 11 wherein said step of forming said mask comprises using a mask used to form said first copper metallization area and a reverse tone resist.

20. The method according to claim 11 wherein said step of etching away said conductive capping layer comprises a Cl or F plasma etch.

21. The method according to claim 11 wherein said step of removing said barrier metal layer is performed before said step of depositing said conductive capping layer.

22. A method of preventing copper contamination of an intermetal dielectric layer during via or dual damascene etching in the fabrication of an integrated circuit device comprising:

forming a first copper metallization in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying said first copper metallization and overlying said dielectric layer;

planarizing said first copper metallization;

etching said first copper metallization to form a recess below the surface of said dielectric layer;

depositing a conductive capping layer overlying said first copper metallization within said recess and overlying said dielectric layer;

partially polishing away said conductive capping layer wherein said conductive capping layer over said first copper metallization is thicker than said conductive capping layer over said dielectric layer;

thereafter etching back said conductive capping layer and said barrier metal layer overlying said dielectric layer leaving said conductive capping layer only over said first copper metallization within said recess;

depositing said intermetal dielectric layer overlying said dielectric layer and said conductive capping layer overlying said first copper metallization;

etching said via or dual damascene opening through said intermetal dielectric layer to said conductive capping layer wherein said conductive capping layer prevents copper contamination of said intermetal dielectric layer during said etching; and

filling said via or dual damascene opening with a metal layer to complete electrical connections in the fabrication of said integrated circuit device.

23. The method according to claim 22 wherein said barrier metal layer comprises one of the group containing:

tantalum, tantalum compounds, titanium, titanium compounds, tungsten, and tungsten compounds.

24. The method according to claim 22 wherein said step of planarizing said first copper metallization comprises polishing said first copper metallization using chemical mechanical polishing (CMP) wherein said barrier metal layer is used as a CMP stop layer.

25. The method according to claim 22 wherein said recess is formed by a wet etch method.

26. The method according to claim 24 wherein said wet etch method comprises CH₂ COOH/NH₄ F or DMSO/CCl₄ chemistry.

27. The method according to claim 22 wherein said conductive capping layer comprises one of the group containing:

tantalum, tantalum compounds, titanium, titanium compounds, tungsten, and tungsten compounds.

28. The method according to claim 22 wherein said step of etching away said conductive capping layer and said barrier metal layer comprises a Cl or F plasma etch.