×

Method to avoid copper contamination on the sidewall of a via or a dual damascene structure

  • US 6,114,243 A
  • Filed: 11/15/1999
  • Issued: 09/05/2000
  • Est. Priority Date: 11/15/1999
  • Status: Expired due to Term
First Claim
Patent Images

1. A method of preventing copper contamination of an intermetal dielectric layer during via or dual damascene etching in the fabrication of an integrated circuit device comprising:

  • forming a first copper metallization in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying said first copper metallization and overlying said dielectric layer;

    planarizing said first copper metallization;

    etching said first copper metallization to form a recess below the surface of said dielectric layer;

    removing said barrier metal layer overlying said dielectric layer;

    depositing a conductive capping layer overlying said first copper metallization within said recess and overlying said dielectric layer;

    coating a spin-on material overlying said conductive capping layer;

    etching back said spin-on material and said conductive capping layer over said dielectric layer;

    thereafter removing all of said spin-on material leaving said conductive capping layer only over said first copper metallization in said recess;

    depositing said intermetal dielectric layer overlying said dielectric layer and said conductive capping layer overlying said first copper metallization;

    etching said via or dual damascene opening through said intermetal dielectric layer to said conductive capping layer wherein said conductive capping layer prevents copper contamination of said intermetal dielectric layer during said etching; and

    filling said via or dual damascene opening with a metal layer to complete electrical connections in the fabrication of said integrated circuit device.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×