Nonvolatile semiconductor memory cell with select gate

• US 6,114,724 A
• Filed: 03/31/1998
• Issued: 09/05/2000
• Est. Priority Date: 03/31/1998
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Ratnakumar, K. Nirmal
• Primary Examiner(s): HARDY, DAVID B
• Application Number:
  US09/052,770
• Time in Patent Office: 889 Days
• Field of Search: 257/314-326, 365/185.18
• US Class Current: 257/326
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

An electrically erasable programmable read only memory (EEPROM) cell including a tunnel dielectric layer formed over a semiconductor substrate. The EEPROM cell may have a floating gate transistor and a select transistor. The floating gate transistor may have a floating gate formed over the tunnel dielectric and a control gate formed over the floating gate. The select transistor may have a first gate formed over the tunnel dielectric and a second gate formed over the first gate. The second gate may be electrically connected to the first gate.

Claims

1. An electrically erasable programmable read only memory (EEPROM) cell comprising:

a semiconductor substrate;

a tunnel dielectric layer formed over the substrate;

a floating gate transistor having a floating gate formed over the tunnel dielectric and a control gate formed over the floating gate; and

a select transistor having a first gate formed over the tunnel dielectric, a second gate formed over the first gate, the second gate electrically connected to the first gate by a conductive layer formed over the first and second gates.

2. The EEPROM cell of claim 1, wherein the floating gate of the floating gate transistor and the first gate of the select transistor comprise a common conductive material.

3. The EEPROM cell of claim 2, wherein the common conductive material comprises polysilicon.

4. The EEPROM cell of claim 1, wherein the control gate of the floating gate transistor and the second gate of the select transistor comprise a common conductive material.

5. The EEPROM cell of claim 4, wherein the common conductive material comprises polysilicon.

6. The EEPROM cell of claim 1, wherein the floating gate transistor has a source region and a drain region in the semiconductor substrate, and wherein the select transistor further comprises a source region and a drain region in the semiconductor substrate, wherein the drain region of the floating gate transistor and the source region of the select transistor region are the same region.

7. The EEPROM cell of claim 1, wherein a source region and a drain region of the floating gate transistor are self-aligned to the floating gate and the control gate, and wherein a source region and a drain region of the select gate transistor are self-aligned to the first and second gates.

8. The EEPROM cell of claim 1, wherein the conductive layer comprises a metal layer.

9. A method of forming an electrically erasable programmable read only memory (EEPROM) cell comprising:

forming a tunnel dielectric over a semiconductor substrate;

forming a floating gate transistor over the tunnel dielectric, the floating gate transistor configured to store charge; and

forming a select transistor over the tunnel dielectric, the select transistor having a first and second gate electrically connected together by a conductive layer formed over the first and second gates.

10. The method of claim 9, wherein the steps of forming the floating gate transistor and the select transistor comprise the steps of:

forming a first conductive layer over the tunnel dielectric;

forming an interlayer dielectric layer over the first conductive layer;

forming a second conductive layer over the interlayer dielectric layer; and

forming a control gate and a floating gate for the floating gate transistor, and the first gate and the second gate for the select transistor.

11. The method of claim 10, wherein the steps of forming the floating gate transistor and the select transistor further comprise the step of forming source and drain regions for the floating gate transistor and the select transistor after forming the second conductive layer.

12. The method of claim 10, wherein the first conductive layer and the second conductive layer comprise polysilicon.

13. The method of claim 12, wherein the third conductive layer comprises a metal layer.

14. The method of claim 10, further comprising the step of depositing the conductive layer over the first and second conductive layers to electrically connect the first and second conductive layers.

15. A memory device comprising:

a first electrically erasable programmable read only memory (EEPROM) cell comprising;

a first select transistor overlying a tunnel dielectric layer and having select and control gates electrically coupled together by a conductive layer formed thereover and being coupled to a first word line; and

a first floating gate transistor, the first floating gate transistor comprising a first control gate and a first floating gate;

a second EEPROM cell coupled to the first EEPROM cell comprising;

a second select transistor coupled to a second independent word line; and

a second floating gate transistor comprising a second control gate and a

second floating gate; and

circuitry coupled to the first floating gate transistor and the second floating gate transistor, the circuitry providing a common read voltage to the first and second control gates for reading data stored on the first floating gate.

16. The memory device of claim 15, wherein the first co ntrol gate and the second control gate are coupled together.

17. The memory device of claim 15, wherein the circuitry comprises a first circuit couple to the first control gate, and a second independent circuit coupled to the second control gate.

18. The memory device of claim 15, further comprising decoder circuitry coupled to the first and second select transistors.

19. The memory device of claim 15, wherein the second select transistor comprises a first gate and a second gate electrically coupled together.

20. A method of programming an electrically erasable programmable read only memory (EEPROM) cell having a select transistor coupled to a bit line and a floating gate transistor having a control gate and a floating gate, the method comprising applying a negative voltage to the control gate of the floating gate transistor, a first positive voltage to the bit line, and a second positive voltage to a gate of the select transistor.

21. The method of claim 20, further comprising the step of floating a source terminal of the floating gate transistor.