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Low voltage MOSFET

  • US 6,114,726 A
  • Filed: 03/11/1998
  • Issued: 09/05/2000
  • Est. Priority Date: 03/11/1998
  • Status: Expired due to Term
First Claim
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1. A low voltage planar power MOSFET comprising:

  • a silicon wafer having a junction receiving surface;

    at least first and second shallow spaced base diffusions of one conductivity type formed in said junction receiving surface and spaced by a common conduction region of said wafer;

    each of said first and second bases having a respective source region of the other conductivity type diffused therein, each source region being substantially wholly contained within a respective base to define at least first and second spaced substantially, coplanar invertible channel regions, said first and second bases having a diffusion depth of less than about 1.5 microns;

    a thin gate insulation layer overlying said invertible channel regions and the surface of said common conduction region between said invertible channel regions; and

    a conductive polysilicon gate electrode layer overlying said gate insulation layer;

    whereinthe polysilicon line width of said polysilicon layer measured in the direction spanning across said common conduction region is between about 0.7 microns and about 3.8 microns.

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