Low voltage MOSFET

• US 6,114,726 A
• Filed: 03/11/1998
• Issued: 09/05/2000
• Est. Priority Date: 03/11/1998
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Barkhordarian, Vrej
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Warren, Matthew E.
• Application Number:
  US09/038,453
• Time in Patent Office: 909 Days
• Field of Search: 257/341, 257/342, 257/343, 257/401
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A low voltage planar MOSFET has a polyline width of less than 3.8 microns and a channel (base) region depth of less than 1.5 microns to produce a device having a reduced figure of merit (or product of Q_GD and R_DSON).

Claims

1. A low voltage planar power MOSFET comprising:

a silicon wafer having a junction receiving surface;

at least first and second shallow spaced base diffusions of one conductivity type formed in said junction receiving surface and spaced by a common conduction region of said wafer;

each of said first and second bases having a respective source region of the other conductivity type diffused therein, each source region being substantially wholly contained within a respective base to define at least first and second spaced substantially, coplanar invertible channel regions, said first and second bases having a diffusion depth of less than about 1.5 microns;

a thin gate insulation layer overlying said invertible channel regions and the surface of said common conduction region between said invertible channel regions; and

a conductive polysilicon gate electrode layer overlying said gate insulation layer;

wherein

the polysilicon line width of said polysilicon layer measured in the direction spanning across said common conduction region is between about 0.7 microns and about 3.8 microns.

2. The MOSFET of claim 1 wherein said gate insulation layer has a thickness less than about 250 Å

.

3. The MOSFET of claim 1 which further includes a source electrode connected to each of said source regions and each of said base regions, and a drain electrode connected to said silicon wafer.

4. The MOSFET of claim 1 wherein said silicon wafer comprises a highly conductive substrate and an epitaxially deposited layer of silicon atop said highly conductive substrate;

said junction receiving surface being defined at the top of said epitaxially deposited layer.

5. The MOSFET of claim 1 wherein each of said bases have a polygonal topology and wherein each of said source regions define annular rings within their respective base.

6. The MOSFET of claim 5 wherein said polysilicon layer has openings therein which are atop and aligned with each of said bases to expose an interior portion of each of said annular source rings and the surface portion of each said base which is enclosed by a respective one of said annular source rings.

7. A planar MOSFET having a breakdown voltage lower than about 30 volts, said MOSFET comprising:

a silicon wafer having a junction receiving surface;

a plurality of symmetrically spaced polygonal base diffusions of one conductivity type formed in said junction receiving surface, each of said bases having a diffusion depth less than about 1.5 microns;

the material of said wafer disposed between said bases defining a common conduction region for the vertical conduction of charge carriers across at least a portion of the thickness of said wafer;

each of said bases having an annular source diffusion therein to define a polygonal invertible channel region around periphery of each of said bases;

a thin gate insulation layer lattice which overlies each of said invertible channel regions and the surface of said common conduction region;

a conductive polysilicon electrode layer in substantial registry with and overlying said gate insulation member;

the polysilicon line width of said polysilicon layer as measured in a direction across said common conduction region being between about 0.7 microns and about 3.8 microns.

8. The MOSFET of claim 7 wherein said gate insulation layer has a thickness less than about 250 Å

.

9. The MOSFET of claim 7 wherein said gate insulation layer has a thickness less than about 250 Å

.

10. The MOSFET of claim 9 wherein said gate insulation layer has a thickness less than about 250 Å

.

11. The MOSFET of claim 7 which further includes a source electrode connected to each of said source regions and each of said base regions, and a drain electrode connected to said silicon wafer.

12. The MOSFET of claim 7 which further includes a source electrode connected to each of said source regions and each of said base regions, and a drain electrode connected to said silicon wafer.

13. The MOSFET of claim 10 which further includes a source electrode connected to each of said source regions and each of said base regions, and a drain electrode connected to said silicon wafer.

14. The MOSFET of claim 7 wherein said silicon wafer comprises a highly conductive substrate on an epitaxially deposited layer of silicon atop said highly conductive substrate;

said junction receiving surface being defined at the top of said epitaxially deposited layer.

15. The MOSFET of claim 7 wherein said silicon wafer comprises a highly conductive substrate on an epitaxially deposited layer of silicon atop said highly conductive substrate;

said junction receiving surface being defined at the top of said epitaxially deposited layer.

16. The MOSFET of claim 8 wherein said silicon wafer comprises a highly conductive substrate on an epitaxially deposited layer of silicon atop said highly conductive substrate;

said junction receiving surface being defined at the top of said epitaxially deposited layer.

17. The MOSFET of claim 10 wherein said silicon wafer comprises a highly conductive substrate on an epitaxially deposited layer of silicon atop said highly conductive substrate;

said junction receiving surface being defined at the top of said epitaxially deposited layer.

18. The MOSFET of claim 7 wherein said polysilicon layer has openings disposed atop and aligned with each of said bases to expose an interior portion of each of said annular source rings and the surface portion of each said base which is enclosed by a respective one of said annular source rings.

19. The MOSFET of claim 11 wherein said polysilicon layer has openings disposed atop and aligned with each of said bases to expose an interior portion of each of said annular source rings and the surface portion of each said base which is enclosed by a respective one of said annular source rings.

20. A power MOSFET comprising:

a polysilicon gate;

a channel region;

a source region; and

a drain region;

said polysilicon gate having a polysilicon line width;

said power MOSFET having a gate to drain capacitance which produces a gate to drain charge QGD;

said power MOSFET having an on resistance between said source region and said drain region expressed as RDSON;

the value of QGD being generally a linear function of said polysilicon line width;

the value of RDSON being non-linearly related to said polysilicon line width; and

said polysilicon line width being between about 0.7 microns and about 3.8 microns, chosen to minimize the product of QGD and RDSON.