Trench isolation of a CMOS structure

• US 6,114,741 A
• Filed: 12/09/1997
• Issued: 09/05/2000
• Est. Priority Date: 12/13/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Loewenstein, Lee M., Joyner, Keith A.
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US08/987,226
• Time in Patent Office: 1,001 Days
• Field of Search: 257/374, 257/369, 257/397, 257/403, 257/506, 257/407, 257/412, 257/616
• US Class Current: 257/506
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

An isolation structure is provided that includes a substrate (10), a refill material such as a refill oxide (22), a gate dielectric such as a gate oxide layer (24), and a gate conductor layer such a polysilicon gate layer (26). The substrate (10) has an active region (12), an active region (14), and a trench region provided between the active region (12) and the active region (14). The active region (14) includes a top corner (32) that is provided where an upper surface of the active region (14) and the trench wall of the trench region that is adjacent to the active region (14) meet. The refill oxide (22) is positioned within the trench region and extends to cover at least a portion of the top corner. The gate oxide layer (24) is provided on the upper surface of the active region (14). The polysilicon gate layer (26) is provided on an upper surface of the gate oxide layer (24).

Claims

1. An isolation structure comprising:

a substrate having a first active region, a second active region, and a trench region having trench walls provided between the first active region and the second active region, the first active region having a top corner provided where an upper surface and the trench wall of the trench region adjacent to the first active region meet;

a refill material provided within the trench region and extending to cover a portion of the top corner;

a gate dielectric layer provided on the upper surface of the first active region; and

a gate conductor layer provided on an upper surface of the gate dielectric layer, wherein the gate conductor layer is separated from the top corner by the refill material.

2. The structure of claim 1, wherein the refill material covers the top corner.

3. The structure of claim 1, wherein the gate conductor layer is a polysilicon gate layer.

4. The structure of claim 1, wherein the top corner is a rounded corner.

5. The structure of claim 1, wherein the substrate is a silicon-on-insulator substrate.

6. The structure of claim 1, wherein the substrate is a silicon bulk substrate.

7. The structure of claim 1, wherein the trench region is about 0.5 micrometers or less in depth.

8. The structure of claim 1, wherein the refill material is deposited anisotropically.

9. The structure of claim 1, wherein the refill material is an oxide.

10. The structure of claim 1, wherein the refill material is a dielectric material.

11. The structure of claim 1, wherein the refill material is an intrinsic semiconductor.

12. The structure of claim 1, wherein the trench region is a shallow trench isolation region.

13. The structure of claim 1, wherein a field-effect transistor is provided in the first active region.

14. The structure of claim 1, wherein the trench region walls are substantially vertical.

15. The structure of claim 1, wherein the trench region walls are angled from vertical.

16. The structure of claim 1, wherein the gate dielectric is a gate oxide.

17. An isolation structure comprising:

a substrate having a first active region, a second active region, and a trench region having trench walls provided between the first active region and the second active region, the first active region having a first top corner provided where an upper surface and the trench wall of the trench region adjacent to the first active region meet, the second active region having a second top corner provided where an upper surface and the trench wall of the trench region adjacent to the second active region meet;

a refill material provided within the trench region and extending to cover a portion of the first top corner and the second top corner;

a first gate dielectric layer provided on the upper surface of the first active region;

a second gate dielectric layer provided on the upper surface of the second active region;

a first gate conductor layer provided on an upper surface of the first gate dielectric layer, wherein the first gate conductor layer is separated from the first top corner by the refill material; and

a second gate conductor layer provided on an upper surface of the second gate dielectric layer, wherein the second gate conductor is separated from the second top corner by the refill material.

18. The structure of claim 17, wherein the refill material covers the first top corner and the second top corner.

19. The structure of claim 17, wherein the first gate conductor layer and the second gate conductor layer are a polysilicon gate layer, the first polysilicon layer serves as the gate for a first metal-oxide field-effect transistor, and the second polysilicon layer serves as the gate for a second metal-oxide field-effect transistor.

20. The structure of claim 17, wherein the refill material is an oxide.

21. The structure of claim 17, wherein the refill material is a dielectric material.

22. The structure of claim 17, wherein the refill material is an intrinsic semiconductor.

23. The structure of claim 17, wherein the first gate dielectric layer and the second gate dielectric layer are oxide layers.