Semiconductor package with translator for connection to an external substrate

• US 6,114,763 A
• Filed: 05/29/1998
• Issued: 09/05/2000
• Est. Priority Date: 05/30/1997
• Status: Expired due to Term

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Smith, John W.
• Primary Examiner(s): Williams, Alexander O.
• Application Number:
  US09/087,739
• Time in Patent Office: 830 Days
• Field of Search: 257/738, 257/734, 257/777, 257/778, 257/692, 257/693, 257/723, 257/780, 257/787, 257/779, 257/786, 257/784
• US Class Current: 257/738
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/0394 Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
• CPC Class Codes: H05K 2201/049 PCB for one component, e.g. for mounting onto mother PCB
• CPC Class Codes: H05K 2201/09472 Recessed pad for surface mounting recess in pad H05K2201/09745; Recessed electrode of component
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 2203/041 Solder preforms in the shape of solder balls soldering leadless components having an array of bottom contacts H05K3/3436
• CPC Class Codes: H05K 3/0058 Laminating printed circuit boards onto other substrates, e.g. metallic substrates H05K1/0281 takes precedence

Abstract

An electronic assembly which includes a semiconductor chip package having an array of package terminals and a translator. The translator has a first array of terminals exposed on a first surface of the translator and a second array of terminals exposed on a second surface of the translator. The pitch of the first array matches the pitch of the semiconductor package. The pitch of the second array matches the pitch of the printed circuit board to which the electronic assembly is to be mounted. The array of package terminals on the semiconductor chip package is aligned with and bonded to the first array of terminals on the translator to form the electronic assembly. The electronic assembly can then be mounted on a board by aligning and bonding the second array of terminals on the translator with the connection pads on the printed circuit board.

Claims

1. An electronic assembly, comprising:

A. a semiconductor chip package having a face surface, a plurality of package terminals disposed on the face surface, and a semiconductor chip, wherein said package terminals are arranged in an array having a first pitch; and

B. a translator, comprising;

a. a flexible, sheet-like support element having a first surface, a second surface opposite the first surface, a peripheral region, and a central region defined by the peripheral region, said peripheral region being more rigid than the central region;

b. a plurality of first translator terminals wherein first translator terminals are disposed on the central region of the support element, exposed at the first surface of the support element, and arranged in an array having said first pitch;

c. a plurality of second translator terminals wherein second translator terminals are exposed at the second surface of the support element and arranged in an array having a pitch which is different than the first pitch and wherein at least some of the second translator terminals are disposed on the peripheral region of the support element; and

d. a plurality of traces electrically interconnecting the package terminals and the first translator terminals.

2. The electronic assembly of claim 1, wherein the peripheral region of the support element is comprised of a flexible, sheet-like layer and a stiffener disposed over the sheet-like layer.

3. The electronic assembly of claim 2, wherein the stiffener has a central hole disposed over the central region of the support element.

4. The electronic assembly of claim 3, further comprising a compliant ring disposed between the stiffener and the flexible, sheet-like layer.

5. The electronic assembly of claim 4, wherein the compliant ring is comprised of a material selected from the group consisting of silicone gels, silicone elastomers and flexiblized epoxies.

6. The electronic assembly of claim 4, further comprising a compliant encapsulant disposed between the semiconductor chip package and the translator.

7. The electronic assembly of claim 1, wherein the array of first translator terminals are disposed on the first surface of the support element.

8. The electronic assembly of claim 1, wherein the array of second translator terminals are disposed on the second surface of the support element.

9. The electronic assembly of claim 7, wherein the semiconductor chip package further comprises a plurality of electrically conductive first joining units, wherein each of the first joining units is connected to one of the package terminals and one of the first translator terminals.

10. The electronic assembly of claim 9, wherein each of the first joining units is a solder ball.

11. The electronic assembly of claim 1, wherein

the semiconductor chip package has a plurality of first joining units,

the support element has a plurality of apertures,

the array of first translator terminals are disposed on the second surface of the support element, and

each of the first translator terminals is disposed over one of the apertures.

12. The electronic assembly of claim 11, wherein the support element further comprises a plurality of holes;

and each of the first translator terminals is disposed over one of the holes, extends inwardly over the hole and is adapted to resiliently engage a respective package terminal.

13. The electronic assembly of claim 1, wherein

the semiconductor chip package further comprises a plurality of electrically conductive first joining units, wherein each of the first joining units is connected to one of the package terminals and one of the first translator terminals;

and

the translator further comprises a plurality of electrically conductive second joining units, wherein each of the second joining units is connected to one of the second translator terminals.

14. The electronic assembly of claim 13, wherein each first joining unit is comprised of a first solder, each second joining unit is comprised of a second solder and the solidus temperature of the first solder is higher than the liquidus temperature of the second solder.

15. The electronic assembly of claim 1, further comprising a heat spreader disposed over the support element.

16. The electronic assembly of claim 1, wherein the first pitch is less than 750 μ

m.

17. The electronic assembly of claim 16, wherein the pitch of the array of second translator terminals is greater than 1000 μ

m.

18. The electronic assembly of claim 1, wherein the semiconductor chip has a plurality of electrically conductive contacts;

and the semiconductor chip package further comprises

a dielectric layer;

wherein the array of package terminals is disposed on the dielectric layer;

a compliant layer disposed between the semiconductor chip and the dielectric layer; and

a plurality of leads extending through the compliant layer, each of said leads connecting one of the contacts to one of the package terminals.

19. The electronic assembly of claim 18, wherein at least some of the leads are fan-out leads.

20. The electronic assembly of claim 19, wherein at least some of the leads are fan-in leads.

21. The electronic assembly of claim 1, wherein at least some of the package terminals are interconnected by traces disposed on the support layer.

22. The electronic assembly of claim 1, wherein the support element further comprises a least one feature selected from the group consisting of ground planes and potential power planes.

23. The electronic assembly of claim 1, wherein the support element further comprises one or more components selected from the group consisting of active and passive microelectronic components.

24. The electronic assembly of claim 1, wherein the translator further comprises a plurality of electrically conductive second joining units, wherein each of the second joining units is connected to one of the second translator terminals;

and the electronic assembly further comprises an external substrate having a top surface and a plurality of electrically conductive connection pads disposed on the top surface, wherein each of the connection pads is electrically interconnected to one of the second joining units.

25. The electronic assembly of claim 1, wherein the semiconductor chip package father comprises a dielectric layer.

26. The electronic assembly of claim 25, wherein the dielectric layer is flexible.

27. The electronic assembly of claim 26, wherein the package terminals are disposed on the flexible dielectric layer.