Image sensor producing at least two integration times from each sensing pixel

• US 6,115,065 A
• Filed: 11/07/1996
• Issued: 09/05/2000
• Est. Priority Date: 11/07/1995
• Status: Expired due to Term

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Fossum, Eric R., Yadid-Pecht, Orly
• Primary Examiner(s): Garber, Wendy
• Assistant Examiner(s): Harrington, Alicia M.
• Application Number:
  US08/744,494
• Time in Patent Office: 1,398 Days
• Field of Search: 348/294, 348/296, 348/308, 348/321, 348/367, 348/269, 348/362, 348/298
• US Class Current: 348/308
• CPC Class Codes: H04N 23/70 Circuitry for compensating brightness variation in the scene
• CPC Class Codes: H04N 25/533 by using differing integration times for different sensor regions
• CPC Class Codes: H04N 25/587 acquired sequentially, e.g. using the combination of odd and even image fields
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

Designs and operational methods to increase the dynamic range of image sensors and APS devices in particular by achieving more than one integration times for each pixel thereof. An APS system with more than one column-parallel signal chains for readout are described for maintaining a high frame rate in readout. Each active pixel is sampled for multiple times during a single frame readout, thus resulting in multiple integration times. The operation methods can also be used to obtain multiple integration times for each pixel with an APS design having a single column-parallel signal chain for readout. Furthermore, analog-to-digital conversion of high speed and high resolution can be implemented.

Claims

1. An imaging device, comprising:

a substrate formed of a semiconductor material;

an image detector array, having a plurality of pixel circuits formed on said substrate, each pixel circuit generating a pixel signal indicative of a pixel of an image;

a first signal buffer, formed on said substrate and coupled to respectively store pixel signals from a first group of said pixel circuits;

a second signal buffer, formed on said substrate and coupled to respectively store pixel signals from a second group of said pixel circuits, wherein said second group is displaced from said first group by a predetermined number of pixel circuits; and

a control circuit coupled to control said image detector array and said first and second signal buffers, said control circuit controlling reading out pixel circuits into said first buffer with a first integration time and controlling reading out pixel circuits into said second buffer with a second integration time different than said first integration time, said first and second buffers storing two different signals with two different integration times for each pixel circuit,

wherein said first and second integration times have a difference which depends on said predetermined number of pixel circuits between said first and second groups,

wherein said control circuit is adapted to select signals with said first integration time from a first group of pixel circuits and signals with said second integration time from a second group of pixel circuits to form said single frame where said first group of pixel circuits receive less light than said second group of pixel circuits.

2. A device as in claim 1, wherein said control circuit is further adapted to simultaneously read two different groups of pixel circuits that are separated by said predetermined number of pixel circuits into said first and second buffers, respectively.

3. A device as in claim 2, wherein said control circuit is further adapted to vary said predetermined number of pixel circuits between two different groups of pixel circuits, that are being simultaneously and respectively read into said first and second buffers, so as to change said difference between said first and second integration times.

4. A device as in claim 2, further comprising:

a first ADC array of analog-to-digital converters respectively coupled to cells of said first buffer array to produce a first portion of digital bits from signals of said first integration time; and

a second ADC array of analog-to-digital converters respectively coupled to cells of said second buffer array to produce a second portion of digital bits from signals of said second integration time,

wherein said control circuit is adapted to combine said first and second portion of digital bits from said first and second ADC arrays of analog-to-digital converters for each pixel into a digital output having a higher resolution than resolutions of said analog-to-digital converters in said first and second ADC arrays.

5. A device as in claim 1, further comprising a transistor amplifier in each pixel circuit.

6. A device as in claim 1, further comprising a buffer memory formed on said substrate adapted to store output signals from each pixel circuit that are generated at different times and respectively have said first and second integration times during a frame readout so as to allow a simultaneous readout of said output signals.

7. A device as in claim 6, wherein said buffer memory has a number of memory cells equal to said predetermined number of pixel circuits between said first and second groups.

8. A device as in claim 1, wherein said controlling circuit has means for enabling each pixel circuit to accumulate signals during consecutive readouts by one of said buffer cells in said first and second signal buffer arrays.

9. A device as in claim 1, further comprising a reset gate in each pixel circuit, wherein said control circuit is operable to control said reset gate to delete accumulated signals upon a completion of a sampling by either said first signal buffer array or said second signal buffer array.

10. A device as in claim 1, wherein said control circuit is further adapted to sample each pixel circuit at least three times with said first and second signal buffer arrays to produce said single frame to generate three sets of data with different integration times for each of said pixel circuits, wherein at least one of said first and second signal buffer arrays operates to sample said pixel circuits twice.

11. An imaging device, comprising:

a substrate;

a detector array having a plurality of pixel circuits formed on said substrate to generate signals indicative of an input scene;

a signal buffer array having a plurality of buffer cells formed on said substrate that are coupled to a patch of pixel circuits to store signals from said patch of pixel circuits; and

a control circuit coupled to control said detector array and said signal buffer array to read each pixel circuit within a patch of pixel circuits at least once into said signal buffer array to have a first integration time, and after sequentially reading a predetermined number of patches, to read each pixel circuit within said patch of pixel circuits at least another time into said signal buffer array to have a second integration time to produce a single output frame, hence each pixel circuit producing at least two different output signals with different integration times,

wherein said first and second integration times have a difference which depends on said predetermined number of patches of pixel circuits,

wherein said control circuit is adapted to select signals with said first integration time from a first group of pixel circuits and signals with said second integration time from a second group of pixel circuits to form said single frame where said first group of pixel circuits receive less light than said second group of pixel circuits.

12. A device as in claim 11, wherein said control circuit is further adapted to vary said predetermined number of patches to change said difference between said first and second integration times.

13. A device as in claim 11, further comprising a transistor amplifier in each pixel circuit.

14. A device as in claim 11, further comprising a buffer memory formed on said substrate adapted to store output signals from each pixel circuit that are generated at different times and respectively have said first and second integration times during a frame readout so as to allow a simultaneous readout of said output signals.

15. A device as in claim 14, wherein said buffer memory has a number of memory cells equal to a number of pixel circuits in said predetermined number of patches.

16. A device as in claim 11, further comprising an ADC array of analog-to-digital converters respectively coupled to cells of said buffer array, each analog-to-digital converter operable to produce a first portion of digital bits from a signal of said first integration time of each pixel and to produce a second portion of digital bits from a signal of said second integration time of each pixel,

wherein said control circuit is adapted to combine said first and second portions of digital bits for each pixel into a digital output having a higher resolution than a resolution of said analog-to-digital converters.

17. A method of using an image array of sensing pixels to detect an optical image, comprising:

receiving light from an image using an image array to produce pixel signals; and

sequentially reading out the pixel signals from the image array to produce a single output frame by reading out two units of sensing pixels that are separated by a predetermined amount of sensing pixels to obtain, for each of the sensing pixels, a first integration-time pixel signal and a second integration-time pixel signal that have different integration times depending on said predetermined amount.

18. A method as in claim 17, further comprising combining at least a portion of the first integration-time signals from a first group of pixels obtained in a frame readout and a portion of the second integration-time pixel signals from a second group of pixels from the same frame readout to form an output frame.

19. A method as in claim 17, wherein said pixel circuits are arranged in columns and rows and further comprising:

providing a first signal readout buffer array having buffer cells that are respectively coupled to pixels in each column;

simultaneously reading a first row into said buffer cells of said first readout buffer array to obtain a set of the first integration-time pixel signals;

sequentially scanning said buffer cells in said first readout buffer array and reading out said set of the first integration-time pixel signals;

selecting a second row in said array which is separated from the first row by the predetermined number of rows;

then simultaneously reading said second row into said buffer cells of said first readout buffer array to obtain a set of the second integration-time pixel signals;

then sequentially scanning said buffer cells in said first readout buffer array and reading out said set of the second integration-time pixel signals; and

repeating each of the above reading process for a row next to the first row and another row next to the second row until all rows are read.

20. A method as in claim 17, wherein said pixel circuits are arranged in columns and rows and further comprising:

providing a first signal readout buffer array having buffer cells that are respectively coupled to pixels in each column;

providing a second signal readout buffer array having buffer cells that are respectively coupled to pixels in each column;

simultaneously reading a first column and a second column into said first readout buffer array and said second readout buffer array, respectively, to obtain a set of the first integration-time pixel signals in said first readout buffer array and a set of the second integration-time pixel signals in said second readout buffer array;

then simultaneously scanning said buffer cells in said first and second readout buffer arrays and reading out said set of first integration-time pixel signals and said set of the second integration-time pixel signals, respectively; and

repeating the above reading and scanning operations to a row next to the first row and another row next to the second row until all rows are read.

21. A method as in claim 17, further comprising:

producing a first portion of digital bits from a first integration-time pixel signal of a pixel;

producing a second portion of digital bits from a second integration-time pixel signal of the same pixel; and

combining the first and second portions of digital bits into a digital output for the same pixel.

22. A method as in claim 17, further comprising depleting a pixel signal in a pixel circuit after reading the pixel circuit to initiate a new integration process.

23. A method as in claim 17, further comprising selecting one of the two different pixel signals from each pixel to form an indicia of the input scene according to an amount of light received by each pixel.