Image sensor with direct digital correlated sampling

• US 6,115,066 A
• Filed: 06/12/1997
• Issued: 09/05/2000
• Est. Priority Date: 06/12/1997
• Status: Expired due to Term

• Current Assignee: Intellectual Discovery Co., Ltd.
• Original Assignee: International Business Machines Corporation
• Inventors: Gowda, Sudhir Muniswamy, Shin, Hyun Jong, Wong, Hon-Sum Philip, Xiao, Peter Hong, Yang, Jungwook
• Primary Examiner(s): HO, TUAN V
• Application Number:
  US08/876,694
• Time in Patent Office: 1,181 Days
• Field of Search: 348/207, 348/241, 348/243, 348/248, 348/294, 348/302, 348/303, 348/304, 348/307, 348/308, 348/300, 348/301, 250/208.1
• US Class Current: 348/308
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

A CMOS image sensor is provided in which correlated double sampling is performed entirely in the digital domain. In an exemplary embodiment, the image sensor includes a plurality of imager cells arranged in rows and columns, where the imager cells of a particular column are coupled to a column data line of that column. Each active imager cell is capable of selectively providing a first output on an associated column data line indicative of a reset level during a first sampling interval. During a second sampling interval, each active imager cell provides a signal output on the associated column data line indicative of an amount of light incident upon that imager cell. At least one analog to digital (A/D) converter is coupled to the column data lines and converts the first and signal outputs on each column data line to first and second digital codes, respectively, to complete a correlated double sampling operation. The invention eliminates the need for analog capacitors to store the reset and signal levels.

Claims

1. An image sensor, comprising:

a plurality of imager cells arranged in rows and columns, with the imager cells of any given column being coupled to a column data line of that column, and each imager cell being operable to selectively provide a first output on an associated column data line indicative of a reset level during a first sampling interval and to provide a signal output on the associated column data line during a second sampling interval indicative of an amount of light incident upon that imager cell, each said imager cell comprises a first transistor operative to selectively set a voltage level at a reference node, and a second transistor having a control terminal coupled to said reference node, and an output terminal coupled to the column data line of the column associated with the particular imager cell, said second transistor providing said first output indicative of potential of said reference node during said first sampling interval in which said first transistors is off, and said signal output indicative of potential of the amount of light incident upon that imager cell during said second sampling interval; and

at least one analog to digital (A/D) converter coupled to said column data lines for converting at least said first output on each column data line to a first corresponding digital code, to enable a subsequent comparison with a second digital code associated with said signal output to complete a correlated double sampling operation.

2. The image sensor of claim 1 wherein said at least one A/D converter also converts said signal output provided during said second sampling interval to said second digital code, and said comparison with said second digital code being a subtraction of a value corresponding to said first digital code from a value corresponding to said second digital code.

3. The image sensor of claim 1 wherein said imager cells within a common row are simultaneously activated for outputting said first and second outputs on associated column data lines, and said at least one A/D converter receiving data from all column data lines simultaneously.

4. The image sensor of claim 1 wherein said at least one A/D converter comprises a plurality of A/D converters, each associated with one of said columns and connected to a corresponding one of said column data lines.

5. The image sensor of claim 4, further comprising a plurality of registers, each coupled to one of said A/D converters, for temporarily storing said first digital codes and subsequently transferring each of said first digital codes to subtraction circuitry for subtracting each of said first digital codes from a corresponding second digital code.

6. The image sensor of claim 1 wherein:

each imager cell includes a photosensitive element for providing a photocharge responsive to incident light, circuit means for selectively transferring the photocharge to a reference node within the imager cell, and a reset switch operable to selectively switch a supply voltage at a low logic slate to the reference node to isolate the reference node from the column bus; and

said first sampling interval follows a shut-off of said reset switch to isolate the reference node from the supply voltage, and said first output is indicative of the reset level at said reference node when said reset switch is off.

7. The image sensor of claim 6, wherein said first sampling interval follows a predetermined column settle interval immediately following said shut-off of said reset switch.

8. The image sensor of claim 6, wherein a charge transfer interval follows said first sampling interval, a predetermined column settle interval immediately follows said charge transfer interval, and said second sampling interval immediately follows said column settle interval.

9. The image sensor of claim 1, including complementary metal oxide semiconductor (CMOS) circuitry for providing timing and control signals to the imager cells.

10. An image sensor, comprising:

a) a plurality of imager cells arranged in rows and columns, with the imager cells of any given column being coupled to a column data line of that column, and each imager cell being operable to selectively provide a first output on an associated column data line indicative of a reset level during a first sampling interval and to provide a signal output on the associated column data line during a second sampling interval indicative of an amount of light incident upon that imager cell, each said imager cell comprising;

i) a photosensitive element providing a photocharge responsive to incoming light;

ii) a first transistor coupled to a row select line carrying a row select signal to imager cells of a common row to selectively activate the imager cells of the common row for image data readout, said first transistor operable to transfer said photocharge towards a reference circuit node within said imager cell responsive to said row select signal;

iii) a second transistor operably coupled to said first transistor, said second transistor operative to selectively set a voltage level at said reference node; and

iv) a third transistor having a control terminal coupled to said reference node, and an output terminal coupled to the column data line of the column associated with the particular imager cell, said third transistor providing said first output indicative of potential of said reference node during said first sampling interval in which said first and second transistors are both off, and said signal output indicative of potential of said reference node during said second sampling interval; and

b) at least one analog to digital (A/D) converter coupled to said column data lines for converting said first and signal outputs on each column data line to first and second digital codes, respectively, to enable a subsequent comparison between the digital codes to complete a correlated double sampling operation.

11. The image sensor of claim 10 wherein said photosensitive element comprises a photodiode.

12. The image sensor of claim 10 wherein said photosensitive element comprises a pinned photodiode.

13. The image sensor of claim 10 wherein during said second sampling interval, said second transistor is on.

14. The image sensor of claim 10 wherein during said second sampling interval, said second transistor is off.

15. The image sensor of claim 10 wherein said first, second and third transistors of each imager cell are MOSFETs.

16. The image sensor of claim 10 wherein conducting terminals of said second and third transistors are connected to a common voltage supply line that supplies voltage to imager cells of a common row.

17. In an image sensor having a plurality of imager cells arranged in at least one row and a plurality of columns, with the imager cells of any given column being coupled to a column data line of that column, a method of performing correlated double sampling, comprising:

selectively activating a plurality of imager cells in a common row, each activated imager cell having a first transistor connected to a voltage reference and a second transistor, said second transistor operatively connected to an associated column data line for providing a first output on the associated column data line indicative of a reset level during a first sampling interval when said first transistor is off and providing a signal output on the associated column data line during a second sampling interval indicative of an amount of light incident upon that imager cell;

converting said first outputs on said column data lines to first digital codes; and

storing said first digital codes to enable subsequent comparisons with corresponding second digital codes associated with said signal outputs to complete the correlated double sampling.

18. The method of claim 17, further comprising converting each said signal output into a corresponding said second digital code during said second sampling interval.

19. The method of claim 17, wherein said step of storing said first digital codes comprises storing said first digital codes in digital registers, and said method further comprising subtracting a value corresponding to said first digital code with a value corresponding to said second digital code to provide an image data output with reset noise removed.