Semiconductor memory device having defect relieving system using data line shift method

• US 6,115,301 A
• Filed: 03/01/1999
• Issued: 09/05/2000
• Est. Priority Date: 03/03/1998
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Namekawa, Toshimasa
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US09/259,274
• Time in Patent Office: 554 Days
• Field of Search: 365/200, 365/225.7, 365/230.03, 365/230.06
• US Class Current: 365/200
• CPC Class Codes: G11C 29/848 by adjacent switching

Abstract

A defective address memory circuit stores the address of a defective data line, and outputs a signal for replacing the defective data line depending on the stored address. Decode circuits constituting a decoder group simultaneously output signals for replacing data lines depending on the output signal from the defective address memory circuit. First and second switch groups shift data lines in the direction of a redundant data line depending on an output signal from the decode circuit to instantaneously replace the defective data line.

Claims

1. A semiconductor memory device comprising:

a memory cell array in which a plurality of memory cells are arranged;

a redundant memory cell array arranged to be adjacent to one end of the memory cell array;

a plurality of data lines, connected to the memory cell array, for transferring data;

a redundant data line, connected to the redundant memory cell array, for transferring data;

a plurality of input/output data lines arranged in correspondence with the plurality of data lines;

a first switch group having a plurality of switches, the switches connecting the data lines to the input/output data lines in correspondence with the data lines;

a second switch group having switches whose number is equal to the number of switches of the first switch group, the second switch group connecting the data lines except for a data line located at the other end of the memory cell array, the redundant data line, and the input/output data line to each other;

a defective address memory circuit for storing an address of a defective data line; and

a decoder group having a plurality of decode circuits, the decode circuits being arranged in correspondence with the switches constituting the first and second switch groups, and simultaneously outputting signals for controlling switches located between the defective data line and the redundant data line of the switches constituting the first and second switch groups depending on the address of the defective data line output from the defective address memory circuit, wherein said switches located between the defective data line and the redundant data line are simultaneously changed in accordance with the signals output from the decode circuits.

2. A device according to claim 1, wherein. the defective address memory circuit comprises:

a plurality of first fuse circuits for storing an address of a defective data line; and

a transfer gate for transferring the address of the defective data line output from the first fuse circuits depending on an input address.

3. A device according to claim 2, wherein each of the first fuse circuits comprises:

a fuse programmed depending on the address of the defective data line; and

a latch circuit for latching a state of the fuse in a power-on state.

4. A device according to claim 1, wherein each of the decode circuits comprises:

an input terminal for receiving the address of the defective data line output from the defective address memory circuit; and

a non-inverted output terminal connected to the switches of the second switch circuit group, and an inverted output terminal connected to the switches of the first switch circuit group, and

each of the decode circuits output a first logic signal from the non-inverted output terminal when the address of the defective data line is equal to or larger than the address of a corresponding data line and output a second logic signal from the non-inverted output terminal when the address of the defective data line is smaller then the address of the corresponding data line.

5. A device according to claim 4, wherein the defective address memory circuit has a second fuse circuit, and the second fuse circuit stores a signal representing replacing of data lines.

6. A device according to claim 5, further comprising

a wiring for connecting the second fuse circuit to a decode circuit, for controlling a switch to which the redundant data line is connected, in the decoder group, and the replacing signal stored in the second fuse circuit is supplied to only the decode circuit for controlling the switch to which the redundant data line is connected through the wiring.

7. A semiconductor memory device comprising:

a memory cell array in which a plurality of memory cells are arranged;

a first redundant memory cell array arranged to be adjacent to the least significant bit of the memory cell array;

a second redundant memory cell array arranged to be adjacent to the most significant bit of the memory cell array;

a plurality of data lines, connected to the memory cell array, for transferring data;

a first redundant data line, connected to the first redundant memory cell array, for transferring data;

a second redundant data line, connected to the second redundant memory cell array, for transferring data;

a plurality of input/output data lines arranged in correspondence with the plurality of data lines;

a switch group having a plurality of switches, the switches having output terminals to which the input/output data lines are connected, of the switches, to the least significant switch having an input terminal to which a data line located at the least significant bit of the memory cell array is connected, a data line adjacent to the data line located at the least significant bit and the first redundant data line being connected, to the most significant switch having an input terminal to which a data line located at the most significant bit of the memory cell array is connected, a data line adjacent to the data line located at the most significant bit and the second redundant data line being connected, and to a plurality of switches having input terminals to which the data lines except for the least significant and most significant data lines are connected, the data line corresponding to the input/output data line and data lines located both the sides of the data line being connected;

a defective address memory circuit for storing an address of a defective data line; and

a decoder group having a plurality of decode circuits, the decode circuits being arranged in correspondence with the switches constituting the switch group, and simultaneously outputting signals for controlling switches located between the defective data line and the redundant data line of the switches constituting the switch group depending on the address of the defective data line output from the defective address memory circuit, wherein said switches located between the defective data line and the redundant data line are simultaneously changed in accordance with the signals output from the decode circuits.

8. A device according to claim 7, wherein

the defective address memory circuit has a first defective address memory circuit for storing an address of a first defective data line, and a second defective address memory circuit for storing an address of a second defective data line.

9. A device according to claim 7, wherein

the decoder group comprises:

a first decoder group for controlling the switches depending on the address of the first defective data line supplied from the first defective address memory circuit to replace the data line in a direction of the second redundant data line; and

a second decoder group for controlling the switches depending on the address of the second defective data line supplied from the second defective address memory circuit to replace the data line in a direction of the first redundant data line.

10. A device according to claim 7, wherein each of the switches is constituted by a plurality of logic circuits.

11. A semiconductor memory device comprising:

a memory cell array in which a plurality of memory cells are arranged;

a redundant memory cell array arranged to be adjacent to one end of the memory cell array;

a plurality of data lines, connected to the memory cell array, for transferring data;

a redundant data line, connected to the redundant memory cell array, for transferring data;

a plurality of input/output data lines arranged in correspondence with the plurality of data lines;

a first selection circuit group having a plurality of selection circuits, the selection circuits connecting the data lines to the corresponding input/output data lines;

a second selection circuit group having selection circuits whose number is equal to the number of selection circuits of the first selection circuit group, the selection circuits of the second selection circuit group connecting the data lines except for a data line located at the other end of the memory cell array, the redundant data line, and the input/output data line to each other;

a defective address memory circuit for storing an address of a defective data line; and

a decoder group having a plurality of decode circuits, the decode circuits being arranged in correspondence with the selection circuits constituting the first and second selection circuit groups, and simultaneously turning off the selection circuit of the first selection circuit group located between the defective data line and the redundant data line and simultaneously turning on the selection circuit of the second selection circuit group.

12. A device according to claim 11, wherein

the defective address memory circuit comprises:

a plurality of first fuse circuits for storing an address of a defective data line; and

a transfer gate for transferring the address of the defective data line output from the first fuse circuits depending on an input address.

13. A device according to claim 12, wherein

each of the first fuse circuits comprises:

a fuse programmed depending on the address of the defective data line; and

a latch circuit for latching a state of the fuse in a power-on state.

14. A device according to claim 11, wherein

each of the decode circuits comprises:

an input terminal for receiving the address of the defective data line output from the defective address memory circuit; and

a non-inverted output terminal connected to the selection circuits of the second selection circuit group, and an inverted output terminal connected to the selection circuits of the first selection circuit group, and

each of the decode circuits output a first logic signal from the non-inverted output terminal when the address of the defective data line is equal to or larger than the address of a corresponding data line and output a second logic signal from the non-inverted output terminal when the address of the defective data line is smaller then the address of the corresponding data line.

15. A device according to claim 14, wherein

the defective address memory circuit has a second fuse circuit, and the second fuse circuit stores a signal representing replacing of data lines.

16. A device according to claim 15, further comprising

a wiring for connecting the second fuse circuit to a decode circuit, for controlling a selection circuit to which the redundant data line is connected, in the decoder group, and the replacing signal stored in the second fuse circuit is supplied to only the decode circuit for controlling the selection circuit to which the redundant data line is connected through the wiring.

17. A device according to claim 11, wherein

each of the selection circuits is a transfer gate constituted by an n-channel MOS transistor and a p-channel MOS transistor.

18. A device according to claim 11, wherein

each of the selection circuits is constituted by a plurality of logic circuits.