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Semiconductor memory device having defect relieving system using data line shift method

  • US 6,115,301 A
  • Filed: 03/01/1999
  • Issued: 09/05/2000
  • Est. Priority Date: 03/03/1998
  • Status: Expired due to Term
First Claim
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1. A semiconductor memory device comprising:

  • a memory cell array in which a plurality of memory cells are arranged;

    a redundant memory cell array arranged to be adjacent to one end of the memory cell array;

    a plurality of data lines, connected to the memory cell array, for transferring data;

    a redundant data line, connected to the redundant memory cell array, for transferring data;

    a plurality of input/output data lines arranged in correspondence with the plurality of data lines;

    a first switch group having a plurality of switches, the switches connecting the data lines to the input/output data lines in correspondence with the data lines;

    a second switch group having switches whose number is equal to the number of switches of the first switch group, the second switch group connecting the data lines except for a data line located at the other end of the memory cell array, the redundant data line, and the input/output data line to each other;

    a defective address memory circuit for storing an address of a defective data line; and

    a decoder group having a plurality of decode circuits, the decode circuits being arranged in correspondence with the switches constituting the first and second switch groups, and simultaneously outputting signals for controlling switches located between the defective data line and the redundant data line of the switches constituting the first and second switch groups depending on the address of the defective data line output from the defective address memory circuit, wherein said switches located between the defective data line and the redundant data line are simultaneously changed in accordance with the signals output from the decode circuits.

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