Method and apparatus for testing a video display chip

• US 6,115,305 A
• Filed: 06/15/1999
• Issued: 09/05/2000
• Est. Priority Date: 06/15/1999
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Rosendale, Glen A., Payne, James E., Hangzo, Nianglamching, Pathak, Saroj
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Le, Thong
• Application Number:
  US09/333,805
• Time in Patent Office: 448 Days
• Field of Search: 365/201, 365/230.06, 365/231, 365/230.08, 365/189.08
• US Class Current: 365/201
• CPC Class Codes: G01R 31/31855 Interconnection testing, e.g. crosstalk, shortcircuits
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters

Abstract

A video chip includes test circuitry for detecting opens and shorts. The circuitry includes a series-connected chain of transistors and a test register. There is a circuit for the column lines and for the row lines. A bit pattern is driven onto the column or the row lines and received in the corresponding test circuitry. The pattern is read out and compared against the input pattern to detect faulty lines.

Claims

1. In a circuit having a plurality of signal lines, a method for testing the electrical integrity of said signal lines, the method comprising:

applying a first voltage potential to a first end of each signal line;

in a chain of series-connected transistors, biasing each transistor thereof with the potential at a second end of each signal line, said chain of transistors having a first end terminal and a second end terminal, said second end terminal capable of being in a high-impedance state or a conductive state;

applying a second voltage potential to said first end terminal of said chain of transistors; and

detecting a potential at said second end terminal of said chain of transistors;

whereby an open in one of said signal lines is indicated by said second end terminal being in a high-impedance state, and the absence of an open in any of said signal lines is indicated by said second end terminal having a potential between ground potential and said second voltage potential.

2. The method of claim 1 further including:

applying a test pattern to said first ends of said signal lines, said test pattern consisting of a combination of logic one'"'"'s and logic zero'"'"'s;

transferring said test pattern into a register, said register disposed at second ends of said signal lines;

reading out the contents of said register; and

comparing the contents of said register against said test pattern;

whereby electrical shorts and electrical opens among said signal lines are indicated by differences between the contents of said register and said test pattern.

3. The method of claim 2 wherein said test pattern comprises alternating one'"'"'s and zero'"'"'s whereby an electrical short between two immediate, neighboring lines is indicated by two consecutive ones in the readout pattern.

4. The method of claim 1 wherein said first potential is greater than any of a plurality of threshold voltages of said transistors.

5. The method of claim 1 wherein said circuit is a video memory device and said signal lines are word select lines and wherein said step of applying a first voltage includes simultaneously activating all of the word select lines in order to transfer said first voltage to said gate terminals of said chain of transistors.

6. In a memory circuit having a matrix of data lines and word lines, a method of testing the electrical integrity of said data lines and said word lines comprising:

driving a first test pattern onto said data lines at a first end thereof;

storing data signals appearing at a second end of said data lines into a first register;

comparing said first test pattern against data latched into said first register;

driving a second test pattern onto said word lines at a first end thereof;

storing data signals appearing at a second end of said word lines into a second register; and

comparing said second test pattern against data latched into said second register.

7. The method of claim 6 further including driving each gate terminal of a series-connected chain of transistors with the voltage potential present at a second end of one of said data lines, applying a voltage at a first end terminal of said chain of transistors and measuring the voltage potential at a second terminal of said chain of transistors.

8. The method of claim 7 further including driving each gate terminal of a second series-connected chain of transistors with the voltage potential present at a second end of one of said word select lines, applying a voltage at a first end terminal of said second chain of transistors and measuring the voltage potential at a second terminal of said second chain of transistors.

9. The method of claim 6 wherein said first and second test patterns comprise alternating logic one'"'"'s and logic zero'"'"'s.

10. A memory circuit comprising:

a plurality of storage elements arranged in row and column fashion;

a column data register having a plurality of outputs coupled to data lines, each data line coupled to a column of said storage elements;

a word selector having a plurality of word select lines, each word select line coupled to a row of said storage elements, each word line having an end distal to said word selector, said word selector being operative to activate any one of said word select lines and further being operative to activate all of said word select lines; and

a series-connected chain of transistors, each having a gate terminal coupled to a distal end of one of said word lines, said chain of transistors having a first end being coupled to a power rail.

11. The memory circuit of claim 10 wherein said transistors are N-channel devices.

12. The memory circuit of claim 10 wherein said word selector includes first circuitry to activate a selected word line, said word selector further including a row data register for receiving a bit pattern and second circuitry for selectively driving said word lines with outputs of said register.

13. The memory circuit of claim 12 further including a row test register having inputs coupled to said distal ends of said word select lines.

14. The memory circuit of claim 10 wherein each data line has an end distal to said column data register, the memory circuit further including a second series-connected chain of transistors, each having a gate terminal coupled to a distal end of one of said data lines, a first end of said chain of transistors being coupled to a first potential.

15. The memory circuit of claim 14 further including a column test register having inputs coupled to said distal ends of said data lines.

16. The memory circuit of claim 14 wherein said transistors of said second chain of transistors are N-channel devices.

17. A test circuitry in a video memory circuit that has a plurality of video storage elements arranged in a matrix form, a plurality of data lines and row select lines coupled to said storage elements, said test circuitry comprising:

a column data register for receiving a test pattern, said column data register having as many bit positions as there are data lines;

a column test register for receiving said test pattern from said column data register via said data lines, said column test register having as many inputs as there are said data lines, said data lines coupling said column test register and said column data register;

a row data register for receiving a test pattern, said row data register having as many bit positions as there are row select lines; and

a row test register for receiving said test pattern from said row data register via said row select lines, said row test register having as many inputs as there are said row select lines, said row select lines coupling said row test register and said row data register;

wherein said column test register and row test register being capable of shifting out their content bits in series.

18. The test circuitry of claim 17 further including:

a first series-connected chain of transistors, each having a gate terminal coupled to one of said data lines; and

a second series-connected chain of transistors, each having a gate terminal coupled to one of said row select lines.

19. The test circuitry of claim 18 wherein each of said first and second chain of transistors includes an end terminal coupled to a power rail.

20. The test circuitry of claim 18 wherein each of said transistors is an N-channel device.