Fair scheduling of ATM cell transmissions during overscheduled conditions
First Claim
1. A method of allocating bandwidth for a plurality of communications channels, comprising the steps of:
- determining an allowed cell rate value for each of the plurality of channels;
issuing a transmission credit for one of the plurality of channels having a lowest timestamp value;
for the channel for which a transmission credit was most recently issued in the issuing step, generating an offset timestamp value based upon a scheduler clock frequency divided by the allowed cell rate value for the channel;
adding a previous timestamp value for the channel, the previous timestamp value corresponding to a time at which the transmission credit was most recently generated, to the offset timestamp value to derive a future credit time value;
comparing the future credit time value with a global time; and
responsive to the comparing step determining that the future credit time value is later than the global time, setting a new timestamp value to the future credit time value; and
responsive to the comparing step determining that the future credit time value is earlier than the global time, adding the offset timestamp value to the global time to generate the new timestamp value; and
repeating the issuing step.
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Abstract
A network hub and Asynchronous Transfer Mode (ATM) translator system (5) for use in a Local Area Network (LAN)-based communications system is disclosed. The network hub and ATM translator system (5) includes a host controller (10) that serves as the LAN hub, and which interfaces with a translator card (15) which includes a segmentation and reassembly device (12) in connection with SONET receive/transmit circuitry (20) that communicates with a transceiver (22) to transmit and receive ATM packet cells over a communications facility (FO). The translator card (15) also includes a scheduler (14) that includes a heap sort state machine (36) which maintains a sorted list of entries, in a heap fashion, in on-chip parameter memory (44) and off-chip parameter memory (18). The entries include, for each ATM channel, a channel identifier and a timestamp that indicates the time at which the next cell for the channel will be due for transmission. A due comparator (40) compares the timestamp of the root value in the heap (i.e., the channel with the next due cell) to a global time generated by a reference timer (38), and indicates to a source behavior processor (24) in the scheduler (14) that a cell is due for transmission. The scheduler than issues a transmit credit for the cell, and communicates this event with the SAR device (12) to effect the transmission as appropriate.
109 Citations
8 Claims
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1. A method of allocating bandwidth for a plurality of communications channels, comprising the steps of:
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determining an allowed cell rate value for each of the plurality of channels; issuing a transmission credit for one of the plurality of channels having a lowest timestamp value; for the channel for which a transmission credit was most recently issued in the issuing step, generating an offset timestamp value based upon a scheduler clock frequency divided by the allowed cell rate value for the channel; adding a previous timestamp value for the channel, the previous timestamp value corresponding to a time at which the transmission credit was most recently generated, to the offset timestamp value to derive a future credit time value; comparing the future credit time value with a global time; and responsive to the comparing step determining that the future credit time value is later than the global time, setting a new timestamp value to the future credit time value; and responsive to the comparing step determining that the future credit time value is earlier than the global time, adding the offset timestamp value to the global time to generate the new timestamp value; and repeating the issuing step. - View Dependent Claims (2, 3, 4)
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5. A network hub and ATM translator system, comprising:
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a host controller, having an interface for receiving local communications; and an ATM translator subsystem, comprising; a transceiver interface, coupled to a high data rate communications facility; segmentation and reassembly circuitry, coupled to the transceiver interface and to the host controller; parameter memory, for storing entries associated with each of a plurality of ATM communications channels; and a scheduler, coupled to the parameter memory and to the segmentation and reassembly processor, for scheduling the transmission of packet cells associated with the plurality of ATM communications channels by a sequence of operations, the scheduler comprising; circuitry for sorting channel entries in the parameter memory, according to a timestamp value associated with each channel, the timestamp value indicating a time at which the transmission of a cell for the associated channel is next due, a root channel entry in the parameter memory corresponding to the next due channel; a reference timer for generating a global time; a comparator for comparing the timestamp value of the root channel entry to the global time; processor circuitry, coupled to the segmentation and reassembly circuitry issuing a transmit credit for the channel associated with the root channel entry; and circuitry for deriving a new timestamp value for the channel associated with the root channel entry, comprising; a divider for generating an offset timestamp value based upon a scheduler clock frequency divided by the allowed cell rate value; an adder for adding the offset timestamp value to a base timestamp value to produce the new timestamp value; a multiplexer, having a first input for receiving the global time from the reference timer, having a second input for receiving the timestamp value of the root channel entry, having an output coupled to the adder to communicate the base timestamp value thereto, and having a control input for selecting either the global time or the timestamp value of the root channel entry for the base timestamp value; and a multiplexer control function, for generating a select signal applied to the control input of the multiplexer, by performing the operations of; generating an offset timestamp value based upon a scheduler clock frequency divided by the allowed cell rate value; adding the timestamp value for the channel associated with the root channel entry to the offset timestamp value to derive a future credit time value; comparing the future credit time value with the global time; and responsive to the comparing step determining that the future credit time value is later than the global time, setting the new timestamp value to the future credit time value; and responsive to the comparing step determining that the future credit time value is earlier than the global time, adding the offset timestamp value to the global time to generate the new timestamp value. - View Dependent Claims (6, 7, 8)
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Specification